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1. 发明授权

US07358817B2 Linearized bias circuit with adaptation 有权
标题翻译：具有适应性的线性化偏置电路
公开(公告)号：US07358817B2
公开(公告)日：2008-04-15
申请号：US11397620
申请日：2006-04-05
申请人： Chi-Hung Kao , Chih-Wei Chen , Cheng-Min Lin , Yun-Shan Chang , Shyh-Chyi Wong
发明人： Chi-Hung Kao , Chih-Wei Chen , Cheng-Min Lin , Yun-Shan Chang , Shyh-Chyi Wong
IPC分类号： H03F3/04
CPC分类号： H03F1/301 , H03F1/302 , H03F3/04 , H03F3/189 , H03F2200/372 , H03F2200/391
摘要： A linearized bias circuit with adaptation resolves the problem happening to the power amplifier with conventional bias circuit that the DC and AC characteristics of the power amplifier shift or even deteriorate due to a temperature variation. The linearized bias circuit with adaptation has a reference voltage source, a first voltage source, a first resistor, a second resistor, a first NPN transistor, a second NPN transistor, and a third NPN transistor. The present invention has the characteristics of bias current temperature compensation, gain and phase compensations to achieve high linearity for the conventional power amplifier and reducing the DC consumption power. At the same time, the quantity of the required elements and layout area in the present invention are small so that the design complexity can be reduced for improving yield, reducing IC layout area, and reducing cost.
摘要翻译：具有适应性的线性化偏置电路利用常规偏置电路解决功率放大器发生的问题，功率放大器的DC和AC特性由于温度变化而偏移甚至劣化。具有自适应的线性化偏置电路具有参考电压源，第一电压源，第一电阻器，第二电阻器，第一NPN晶体管，第二NPN晶体管和第三NPN晶体管。本发明具有偏置电流温度补偿，增益和相位补偿的特点，可实现传统功率放大器的高线性度，降低直流消耗功率。同时，本发明所需元件的数量和布局面积小，从而可以降低设计复杂度，从而提高产量，降低IC布局面积，降低成本。

2. 发明申请

US20060226911A1 Linearized bias circuit with adaptation 有权
标题翻译：具有适应性的线性化偏置电路
公开(公告)号：US20060226911A1
公开(公告)日：2006-10-12
申请号：US11397620
申请日：2006-04-05
申请人： Chi-Hung Kao , Chih-Wei Chen , Cheng-Min Lin , Yun-Shan Chang , Shyh-Chyi Wong
发明人： Chi-Hung Kao , Chih-Wei Chen , Cheng-Min Lin , Yun-Shan Chang , Shyh-Chyi Wong
IPC分类号： H03F3/04
CPC分类号： H03F1/301 , H03F1/302 , H03F3/04 , H03F3/189 , H03F2200/372 , H03F2200/391
摘要： A linearized bias circuit with adaptation resolves the problem happening to the power amplifier with conventional bias circuit that the DC and AC characteristics of the power amplifier shift or even deteriorate due to a temperature variation. The linearized bias circuit with adaptation has a reference voltage source, a first voltage source, a first resistor, a second resistor, a first NPN transistor, a second NPN transistor, and a third NPN transistor. The present invention has the characteristics of bias current temperature compensation, gain and phase compensations to achieve high linearity for the conventional power amplifier and reducing the DC consumption power. At the same time, the quantity of the required elements and layout area in the present invention are small so that the design complexity can be reduced for improving yield, reducing IC layout area, and reducing cost.
摘要翻译：具有适应性的线性化偏置电路利用常规偏置电路解决功率放大器发生的问题，功率放大器的DC和AC特性由于温度变化而偏移甚至劣化。具有自适应的线性化偏置电路具有参考电压源，第一电压源，第一电阻器，第二电阻器，第一NPN晶体管，第二NPN晶体管和第三NPN晶体管。本发明具有偏置电流温度补偿，增益和相位补偿的特点，可实现传统功率放大器的高线性度，降低直流消耗功率。同时，本发明所需元件的数量和布局面积很小，从而可以降低设计复杂度，从而提高产量，降低IC布局面积，降低成本。

3. 发明授权

US07437131B2 Active mixer with self-adaptive bias feedback 有权
标题翻译：具有自适应偏置反馈的有源混频器
公开(公告)号：US07437131B2
公开(公告)日：2008-10-14
申请号：US11267503
申请日：2005-11-07
申请人： Ching-Kuo Wu , Chih-Wei Chen , Yun-Shan Chang , Shyh-Chyi Wong
发明人： Ching-Kuo Wu , Chih-Wei Chen , Yun-Shan Chang , Shyh-Chyi Wong
IPC分类号： H04B1/04
CPC分类号： H03D7/1433 , H03D7/1408 , H03D7/1425 , H03D7/145 , H03D7/1458 , H03D7/1491 , H03D2200/0043
摘要： An active mixer with self-adaptive bias feedback is described and resolves a poor linearity, inconvenient design of a bias circuit, and other defects of a conventional mixer. The dual self-feedback bias structure according to this invention is used. The active mixer with self-adaptive bias feedback has a power supply, an RF input match/drive unit, a local oscillator input match/drive unit, a mixer core unit, a self-adaptive twin bias circuit and an IF output match/buffer unit. This invention improves the linearity of a conventional mixer and does not affect other characteristics. There are fewer components in this invention; an area of the mixer is thus smaller. Further, this invention may improve temperature response, increase yield factor, and lower unit cost. The dual self-feedback bias structure is designed for further application to other semiconductor manufacturing processes, components, and microwave products.
摘要翻译：描述了具有自适应偏置反馈的有源混频器，并且解决了差的线性度，偏置电路的不方便设计以及常规混频器的其它缺陷。使用根据本发明的双重自反馈偏置结构。具有自适应偏置反馈的有源混频器具有电源，RF输入匹配/驱动单元，本地振荡器输入匹配/驱动单元，混频器核心单元，自适应双偏置电路和IF输出匹配/缓冲器单元。本发明改进了常规混合器的线性度并且不影响其它特性。本发明中的组分少; 因此混频器的面积更小。此外，本发明可以改善温度响应，提高产量因子和降低单位成本。双自反馈偏置结构被设计用于进一步应用于其他半导体制造工艺，部件和微波产品。

4. 发明申请

US20060135106A1 Active mixer with self-adaptive bias feedback 有权
标题翻译：具有自适应偏置反馈的有源混频器
公开(公告)号：US20060135106A1
公开(公告)日：2006-06-22
申请号：US11267503
申请日：2005-11-07
申请人： Ching-Kuo Wu , Chih-Wei Chen , Yun-Shan Chang , Shyh-Chyi Wong
发明人： Ching-Kuo Wu , Chih-Wei Chen , Yun-Shan Chang , Shyh-Chyi Wong
IPC分类号： H04B1/18 , H04B1/26
CPC分类号： H03D7/1433 , H03D7/1408 , H03D7/1425 , H03D7/145 , H03D7/1458 , H03D7/1491 , H03D2200/0043
摘要： An active mixer with self-adaptive bias feedback is described and resolves a poor linearity, inconvenient design of a bias circuit, and other defects of a conventional mixer. The dual self-feedback bias structure according to this invention is used. The active mixer with self-adaptive bias feedback has a power supply, an RF input match/drive unit, a local oscillator input match/drive unit, a mixer core unit, a self-adaptive twin bias circuit and an IF output match/buffer unit. This invention improves the linearity of a conventional mixer and does not affect other characteristics. There are fewer components in this invention; an area of the mixer is thus smaller. Further, this invention may improve temperature response, increase yield factor, and lower unit cost. The dual self-feedback bias structure is designed for further application to other semiconductor manufacturing processes, components, and microwave products.
摘要翻译：描述了具有自适应偏置反馈的有源混频器，并且解决了差的线性度，偏置电路的不方便设计以及常规混频器的其它缺陷。使用根据本发明的双重自反馈偏置结构。具有自适应偏置反馈的有源混频器具有电源，RF输入匹配/驱动单元，本地振荡器输入匹配/驱动单元，混频器核心单元，自适应双偏置电路和IF输出匹配/缓冲器单元。本发明改进了常规混合器的线性度并且不影响其它特性。本发明中的组分少; 因此混频器的面积更小。此外，本发明可以改善温度响应，提高产量因子和降低单位成本。双自反馈偏置结构被设计用于进一步应用于其他半导体制造工艺，部件和微波产品。

5. 发明授权

US08026767B2 Adaptive bias circuit and system thereof 有权
标题翻译：自适应偏置电路及其系统
公开(公告)号：US08026767B2
公开(公告)日：2011-09-27
申请号：US12545084
申请日：2009-08-21
申请人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
发明人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
IPC分类号： H03F3/04
CPC分类号： H03F1/0266 , H03F1/56 , H03F3/195 , H03F3/245 , H03F2200/108 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03F2200/555
摘要： An adaptive bias circuit which provides a more sensitive adaptive bias current with respect to power level is used for biasing an electronic circuit. The adaptive bias circuit has a first transistor coupled to a power supply, a voltage bias circuit coupled to the first transistor and the power supply biasing the first transistor, and a first power coupling module coupled to the first transistor and the electronic circuit for coupling a portion of input signal power to the first transistor. A second transistor is coupled to the first transistor and the power supply to increase the current gain of the adaptive bias circuit, and a second current coupling module is coupled to the second transistor and the electronic circuit to provide adaptive bias current to the electronic circuit.
摘要翻译：使用相对于功率电平提供更灵敏的自适应偏置电流的自适应偏置电路用于偏置电子电路。自适应偏置电路具有耦合到电源的第一晶体管，耦合到第一晶体管的电压偏置电路和偏置第一晶体管的电源，以及耦合到第一晶体管和电子电路的第一功率耦合模块，用于耦合输入信号功率的一部分到第一晶体管。第二晶体管耦合到第一晶体管和电源以增加自适应偏置电路的电流增益，并且第二电流耦合模块耦合到第二晶体管和电子电路以向电子电路提供自适应偏置电流。

6. 发明申请

US20110043287A1 ADAPTIVE BIAS CIRCUIT AND SYSTEM THEREOF 有权
标题翻译：自适应偏置电路及其系统
公开(公告)号：US20110043287A1
公开(公告)日：2011-02-24
申请号：US12545084
申请日：2009-08-21
申请人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
发明人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
IPC分类号： H03F3/04
CPC分类号： H03F1/0266 , H03F1/56 , H03F3/195 , H03F3/245 , H03F2200/108 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03F2200/555
摘要： An adaptive bias circuit which provides a more sensitive adaptive bias current with respect to power level is used for biasing an electronic circuit. The adaptive bias circuit has a first transistor coupled to a power supply, a voltage bias circuit coupled to the first transistor and the power supply biasing the first transistor, and a first power coupling module coupled to the first transistor and the electronic circuit for coupling a portion of input signal power to the first transistor. A second transistor is coupled to the first transistor and the power supply to increase the current gain of the adaptive bias circuit, and a second current coupling module is coupled to the second transistor and the electronic circuit to provide adaptive bias current to the electronic circuit.
摘要翻译：使用相对于功率电平提供更灵敏的自适应偏置电流的自适应偏置电路用于偏置电子电路。自适应偏置电路具有耦合到电源的第一晶体管，耦合到第一晶体管的电压偏置电路和偏置第一晶体管的电源，以及耦合到第一晶体管和电子电路的第一功率耦合模块，用于耦合输入信号功率的一部分到第一晶体管。第二晶体管耦合到第一晶体管和电源以增加自适应偏置电路的电流增益，并且第二电流耦合模块耦合到第二晶体管和电子电路以向电子电路提供自适应偏置电流。

7. 发明授权

US07692493B1 High-efficiency single to differential amplifier 有权
标题翻译：高效单差分放大器
公开(公告)号：US07692493B1
公开(公告)日：2010-04-06
申请号：US12356537
申请日：2009-01-21
申请人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
发明人： Chih-Wei Chen , Chuan-Jane Chao , Shyh-Chyi Wong
IPC分类号： H03F3/04
CPC分类号： H03F3/191 , H03F1/0261 , H03F3/45085 , H03F3/45098 , H03F2203/45166
摘要： A high-efficiency single-to-differential amplifier has a first transistor acting as a first amplification stage. A second transistor, a third transistor, a first choke, a second choke, and a first capacitor form a second single-to-differential amplification stage. The first amplification stage receives and amplifies an input signal, outputs the amplified signal to the second single-to-differential amplification stage through a coupling module, and concurrently provides DC bias current to the second single-to-differential amplification stage through a tank. The second single-to-differential amplification stage reuses DC current of the first amplification stage, amplifies the output signal of the first amplification stage, and transfers it to a differential output.
摘要翻译：高效率的单对差分放大器具有作为第一放大级的第一晶体管。第二晶体管，第三晶体管，第一扼流圈，第二扼流圈和第一电容器形成第二单差放大级。第一放大级接收并放大输入信号，通过耦合模块将放大的信号输出到第二单差分放大级，并通过一个容器向第二单差放大级提供DC偏置电流。第二单差分放大级重新利用第一放大级的直流电流，放大第一放大级的输出信号，并将其传送到差分输出。

8. 发明申请

US20090213940A1 Error Resilient Video Transmission Using Instantaneous Receiver Feedback and Channel Quality Adaptive Packet Retransmission 有权
标题翻译：使用瞬时接收机反馈和信道质量自适应分组重传的弹性视频传输错误
公开(公告)号：US20090213940A1
公开(公告)日：2009-08-27
申请号：US12110570
申请日：2008-04-28
申请人： Eckehard Goetz Steinbach , Wei-Kung Deng , Shyh-Chyi Wong
发明人： Eckehard Goetz Steinbach , Wei-Kung Deng , Shyh-Chyi Wong
IPC分类号： H04N7/26
CPC分类号： H04N19/895 , H04N19/124 , H04N19/132 , H04N19/166 , H04N19/176
摘要： Systems and methods for delivering real-time video imagery to a receiver over a channel. A current video frame is captured and digitized. The digitized frame is divided into a plurality of macroblocks. For each macroblock an intra, inter or skip mode coding mode is determined. Based on instantaneous feedback received from a receiver regarding successfully received video packets for a prior video frame, a quantization parameter is set and the macroblocks are encoded in accordance with their respective selected coding mode. Synchronized error concealment is performed at both the encoder and decoder sides of the system and retransmission of lost video packets, using an adaptive retransmission scheme, are performed in accordance with the instantaneous feedback from the receiver.
摘要翻译：通过频道将实时视频图像传送到接收器的系统和方法。当前的视频帧被捕获并数字化。数字化帧被分成多个宏块。对于每个宏块，确定帧内，帧间或跳过模式编码模式。基于从接收机接收到的关于先前视频帧的成功接收的视频分组的瞬时反馈，设置量化参数，并且根据它们各自选择的编码模式对宏块进行编码。在系统的编码器和解码器侧执行同步错误隐藏，并且根据来自接收机的瞬时反馈来执行使用自适应重传方案的丢失视频分组的重传。

9. 发明授权

US07061056B2 High fMAX deep submicron MOSFET 失效
标题翻译：高fMAX深亚微米MOSFET
公开(公告)号：US07061056B2
公开(公告)日：2006-06-13
申请号：US10623907
申请日：2003-07-18
申请人： Chao-Chieh Tsai , Shyh-Chyi Wong , Chung-Long Chang
发明人： Chao-Chieh Tsai , Shyh-Chyi Wong , Chung-Long Chang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28114 , H01L21/76819 , H01L21/76895 , H01L29/42376 , H01L29/4238 , H01L29/665
摘要： A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET. Whereby the width of the metal gate portion reduces Rg and increases the fMAX of the high fMAX deep submicron MOSFET.
摘要翻译：一种形成高密度亚微米级MOSFET的方法，包括以下步骤。提供其上形成有MOSFET的衬底。 MOSFET具有源极和漏极，并且在栅极上方包括硅化物部分。在衬底和MOSFET上形成第一ILD层。将第一ILD层平坦化以在栅电极上露出硅化物部分。金属栅极部分形成在平坦化的第一ILD层之上并且在栅电极上方的硅化物部分之上。金属栅极部分的宽度基本上大于栅电极上的硅化物部分的宽度。第二ILD层形成在金属栅极部分和第一ILD层上。通过与金属栅极部分接触的第二ILD层形成第一金属触点，并且通过接触漏极的第二和第一ILD层形成第二金属触点，从而形成高的最大深度亚微米MOSFET。由此金属栅极部分的宽度减小R＆lt;＆gt;并增加高的最大深亚微米MOSFET的最大最大值。

10. 发明授权

US07030728B2 Layout and method to improve mixed-mode resistor performance 有权
标题翻译：布局和方法来提高混合电阻的性能
公开(公告)号：US07030728B2
公开(公告)日：2006-04-18
申请号：US10831848
申请日：2004-04-26
申请人： Kong-Beng Thei , Chih-Hsien Lin , Shyh-Chyi Wong
发明人： Kong-Beng Thei , Chih-Hsien Lin , Shyh-Chyi Wong
IPC分类号： H01C1/012
CPC分类号： H01L28/20 , H01C7/006 , H01C17/0656 , H01C17/075 , H01L27/0802 , Y10T29/49082 , Y10T29/49087 , Y10T29/49098
摘要： A resistor layout and method of forming the resistor are described which achieves improved resistor characteristics, such as resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first resistor element, a second resistor element, a third resistor element, a fourth resistor element, and a fifth resistor element. A layer of protective dielectric is then formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide, such as titanium silicide or cobalt silicide, using a silicidation process. The higher conductivity silicide forms low resistance contacts between the second and fourth resistor elements and between the third and fifth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element, which is the main resistor element. This provides low voltage coefficient of resistance thermal process stability for the resistor.
摘要翻译：描述了形成电阻器的电阻器布局和方法，其实现了电阻器稳定性和电阻电压系数的改善的电阻器特性。电阻器由诸如掺杂硅或多晶硅的导电材料形成。电阻器具有矩形的第一电阻元件，第二电阻元件，第三电阻元件，第四电阻元件和第五电阻元件。然后在第一，第二和第三电阻器元件上形成保护电介质层，留下第四和第五电阻元件。然后，使用硅化工艺将暴露的第四和第五电阻器元件中的导电材料改变为硅化物，例如硅化钛或硅化钴。较高电导率的硅化物在第二和第四电阻元件之间以及第三和第五电阻器元件之间形成低电阻触点。第二和第三电阻器元件比第一电阻器元件宽，并且向作为主电阻器元件的第一电阻器元件提供低电阻触点。这为电阻器提供了低电阻系数的电阻热处理稳定性。

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