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1. 发明授权

US07122878B2 Method to fabricate high reliable metal capacitor within copper back-end process 有权
标题翻译：在铜后端工艺中制造高可靠性金属电容器的方法
公开(公告)号：US07122878B2
公开(公告)日：2006-10-17
申请号：US11143229
申请日：2005-06-02
申请人： Chi-Feng Huang , Chun-Hon Chen , Shy Chy Wong , Chih Hsien Lin
发明人： Chi-Feng Huang , Chun-Hon Chen , Shy Chy Wong , Chih Hsien Lin
IPC分类号： H01L29/00
CPC分类号： H01L28/60 , H01L21/28568 , H01L21/3143 , H01L21/31608 , H01L21/31637 , H01L21/3185 , H01L21/76838 , H01L28/75
摘要： A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, ac contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.
摘要翻译：提供了一种用于创建高可靠性金属电容器作为后端处理的一部分的新方法。产生金属互连的第一层，在要与其形成电容器的第一互连层的表面上提供交流接触点。使用用于底板的TaN，高介电常数介电材料电容器和使用TaN作为顶板，形成覆盖接触点的铜互连。沉积的层被图案化和蚀刻，在电容器的侧壁上形成间隔层以防止电容器侧壁泄漏。然后通过首先沉积一层蚀刻停止材料形成顶部互连金属，用于电容器和设置在下面的衬底中的半导体器件的进一步互连。

2. 发明授权

US06916722B2 Method to fabricate high reliable metal capacitor within copper back-end process 有权
标题翻译：在铜后端工艺中制造高可靠性金属电容器的方法
公开(公告)号：US06916722B2
公开(公告)日：2005-07-12
申请号：US10307617
申请日：2002-12-02
申请人： Chi-Feng Huang , Chun-Hon Chen , Shy-Chy Wong , Chih Hsien Lin
发明人： Chi-Feng Huang , Chun-Hon Chen , Shy-Chy Wong , Chih Hsien Lin
IPC分类号： H01L21/02 , H01L21/285 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768 , H01L21/20
CPC分类号： H01L28/60 , H01L21/28568 , H01L21/3143 , H01L21/31608 , H01L21/31637 , H01L21/3185 , H01L21/76838 , H01L28/75
摘要： A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, a contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.
摘要翻译：提供了一种用于创建高可靠性金属电容器作为后端处理的一部分的新方法。产生第一层金属互连，在第一层互连层的表面上提供一个接触点，与其形成电容器。使用用于底板的TaN，高介电常数介电材料电容器和使用TaN作为顶板，形成覆盖接触点的铜互连。沉积的层被图案化和蚀刻，在电容器的侧壁上形成间隔层以防止电容器侧壁泄漏。然后通过首先沉积一层蚀刻停止材料形成顶部互连金属，以便电容器和设置在下面的衬底中的半导体器件进一步互连。

3. 发明授权

US06583491B1 Microelectronic fabrication having microelectronic capacitor structure fabricated therein 有权
标题翻译：在其中制造具有微电子电容器结构的微电子制造
公开(公告)号：US06583491B1
公开(公告)日：2003-06-24
申请号：US10143162
申请日：2002-05-09
申请人： Chi-Feng Huang , Chun-Hon Chen
发明人： Chi-Feng Huang , Chun-Hon Chen
IPC分类号： H01L2900
CPC分类号： H01L28/55
摘要： Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure upon a conductor stud layer formed into a first via defined by a patterned dielectric layer to reach a one of a pair of patterned conductor layers within the microelectronic fabrication prior to forming through the patterned dielectric layer a second via to reach the other of the pair of patterned conductor layers within the microelectronic fabrication. The method provides the resulting microelectronic fabrication with enhanced reliability and performance.
摘要翻译：在制造微电子制造的方法和使用该方法制造的微电子制造中，在微电子制造中形成电容器结构，该电容器结构形成在由图案化的介电层限定的第一通孔中的导体柱层上，以达到在微电子制造之前，在通过图案化的电介质层形成第二通孔以达到微电子制造中的一对图案化导体层中的另一个之前，微电子制造中的一对图案化导体层。该方法提供了所得的微电子制造，具有增强的可靠性和性能。

4. 发明申请

US20050221575A1 Novel method to fabricate high reliable metal capacitor within copper back-end process 有权
标题翻译：在铜后端工艺中制造高可靠性金属电容器的新方法
公开(公告)号：US20050221575A1
公开(公告)日：2005-10-06
申请号：US11143229
申请日：2005-06-02
申请人： Chi-Feng Huang , Chun-Hon Chen , Shy-Chy Wong , Chih Lin
发明人： Chi-Feng Huang , Chun-Hon Chen , Shy-Chy Wong , Chih Lin
IPC分类号： H01L21/02 , H01L21/285 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/60 , H01L21/28568 , H01L21/3143 , H01L21/31608 , H01L21/31637 , H01L21/3185 , H01L21/76838 , H01L28/75
摘要： A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, ac contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.
摘要翻译：提供了一种用于创建高可靠性金属电容器作为后端处理的一部分的新方法。产生金属互连的第一层，在要与其形成电容器的第一互连层的表面上提供交流接触点。使用用于底板的TaN，高介电常数介电材料电容器和使用TaN作为顶板，形成覆盖接触点的铜互连。沉积的层被图案化和蚀刻，在电容器的侧壁上形成间隔层以防止电容器侧壁泄漏。然后通过首先沉积一层蚀刻停止材料形成顶部互连金属，以便电容器和设置在下面的衬底中的半导体器件进一步互连。

5. 发明授权

US06734079B2 Microelectronic fabrication having sidewall passivated microelectronic capacitor structure fabricated therein 有权
标题翻译：具有在其中制造的侧壁钝化微电子电容器结构的微电子制造
公开(公告)号：US06734079B2
公开(公告)日：2004-05-11
申请号：US10170840
申请日：2002-06-13
申请人： Chi-Feng Huang , Shyh-Chyi Wang , Chih-Hsien Lin , Chun-Hon Chen , Tien-I Bao , Syun-Ming Jang
发明人： Chi-Feng Huang , Shyh-Chyi Wang , Chih-Hsien Lin , Chun-Hon Chen , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L2120
CPC分类号： H01L28/55 , Y10S438/945
摘要： Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure which comprises a first capacitor plate layer having formed thereupon a capacitor dielectric layer in turn having formed thereupon a second capacitor plate layer, wherein each of the foregoing layers having an exposed sidewall to thus form a series of exposed sidewalls. The capacitor structure also comprises a silicon oxide dielectric layer formed passivating the series of exposed sidewalls of the first capacitor plate layer, the capacitor dielectric layer and the second capacitor plate layer a silicon oxide dielectric layer.
摘要翻译：在制造微电子制造的方法和使用该方法制造的微电子制造中，在微电子制造中形成电容器结构，该电容器结构包括依次形成有电容器电介质层的第一电容器板层，其上形成有第二电容器板层，其中每个前述层具有暴露的侧壁，从而形成一系列暴露的侧壁。电容器结构还包括形成钝化第一电容器板层的一系列暴露的侧壁，电容器介电层和第二电容器板层的氧化硅介电层的氧化硅介电层。

6. 发明授权

US09159802B2 MOS devices with mask layers and methods for forming the same 有权
标题翻译：具有掩模层的MOS器件及其形成方法
公开(公告)号：US09159802B2
公开(公告)日：2015-10-13
申请号：US13471270
申请日：2012-05-14
申请人： Chu-Fu Chen , Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang
发明人： Chu-Fu Chen , Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66
CPC分类号： H01L29/66492 , H01L21/28518 , H01L21/76897 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
摘要翻译：器件包括衬底，衬底上的栅极电介质，以及栅极电介质上的栅电极。漏极区域和源极区域设置在栅电极的相对侧上。绝缘区域设置在基板中，其中绝缘区域的边缘与漏极区域和源极区域的边缘接触。介电掩模包括与漏极区域和绝缘区域的相邻部分之间的第一界面重叠的部分。漏极硅化物区域设置在漏极区域之上，其中硅化物区域的边缘基本上与电介质掩模的第一部分的边缘对准。

7. 发明授权

US09022525B2 Page-width array printing device 有权
标题翻译：页宽阵列打印设备
公开(公告)号：US09022525B2
公开(公告)日：2015-05-05
申请号：US13957501
申请日：2013-08-02
申请人： Ta-Wei Hsueh , Ying-Lun Chang , Hsien-Chung Tai , Yung-Lung Han , Chi-Feng Huang
发明人： Ta-Wei Hsueh , Ying-Lun Chang , Hsien-Chung Tai , Yung-Lung Han , Chi-Feng Huang
IPC分类号： B41J2/155 , B41J2/14
CPC分类号： B41J2/155 , B41J2/14145 , B41J2002/14459 , B41J2202/20
摘要： A page-width array printing device includes a page-width array printing mechanism including at least one page-width array printing module. The page-width array printing module includes a printing platform, a first page-width array printing unit and a second page-width array printing unit. The first page-width array printing unit includes a plurality of first inkjet cartridges. The second page-width array printing unit includes a plurality of second inkjet cartridges. The first page-width array printing unit and the second page-width array printing unit are in parallel with each other. The first inkjet cartridges and the second inkjet cartridges are staggered and independently and detachably disposed on the printing platform. Each of the first inkjet cartridges and the second inkjet cartridges includes an inkjet chip. The inkjet chip includes four ink supply channels and a plurality of nozzles so as to perform a monochromatic or polychromatic page-width array printing operation.
摘要翻译：页宽阵列打印设备包括具有至少一个页宽阵列打印模块的页宽阵列打印机构。页宽阵列打印模块包括打印平台，第一页宽阵列打印单元和第二页宽阵列打印单元。第一页宽阵列印刷单元包括多个第一喷墨盒。第二页宽阵列印刷单元包括多个第二喷墨盒。第一页宽阵列打印单元和第二页宽阵列打印单元彼此并联。第一喷墨墨盒和第二喷墨墨盒是交错的并且可独立且可拆卸地设置在打印平台上。第一喷墨盒和第二喷墨盒中的每一个包括喷墨芯片。喷墨芯片包括四个供墨通道和多个喷嘴，以执行单色或多色页宽阵列打印操作。

8. 发明授权

US08921978B2 Dual DNW isolation structure for reducing RF noise on high voltage semiconductor devices 有权
标题翻译：双DNW隔离结构，用于降低高压半导体器件的RF噪声
公开(公告)号：US08921978B2
公开(公告)日：2014-12-30
申请号：US13347031
申请日：2012-01-10
申请人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Hsiao-Chun Lee
发明人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Hsiao-Chun Lee
IPC分类号： H01L21/70
CPC分类号： H01L21/823892 , H01L21/761 , H01L27/0928
摘要： An isolation structure in a semiconductor device absorbs electronic noise and prevents substrate leakage currents from reaching other devices and signals. The isolation structure provides a duality of deep N-well (“DNW”) isolation structures surrounding an RF device or other source of electronic noise. The DNW isolation structures extend into the substrate at a depth of at least about 2.5 μm and may be coupled to VDD. P+ guard rings are also provided in some embodiments and are provided inside, outside or between the dual DNW isolation structures.
摘要翻译：半导体器件中的隔离结构吸收电子噪声并防止衬底漏电流到达其它器件和信号。隔离结构提供了围绕RF器件或其他电子噪声源的深N阱（“DNW”）隔离结构的二元性。 DNW隔离结构在至少约2.5μm的深度延伸到衬底中，并且可以耦合到VDD。在一些实施例中还提供了P +保护环，并且设置在双DNW隔离结构内部，外部或之间。

9. 发明申请

US20140001518A1 Integrated Circuit Devices with Well Regions and Methods for Forming the Same 审中-公开
标题翻译：具有井区的集成电路器件及其形成方法
公开(公告)号：US20140001518A1
公开(公告)日：2014-01-02
申请号：US13539027
申请日：2012-06-29
申请人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Mingo Liu
发明人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Mingo Liu
IPC分类号： H01L27/07 , H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/07 , H01L27/085 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/732 , H01L29/7327 , H01L29/808 , H01L29/861 , H01L29/93
摘要： A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.
摘要翻译：一种方法包括在衬底中形成第一导电类型的深阱区域，注入深阱区域的一部分以形成第一栅极，以及植入深阱区域以形成阱区域。阱区和第一栅极是与第一导电类型相反的第二导电类型。执行注入以在第一栅极上形成第一导电类型的沟道区。植入覆盖沟道区域的深阱区域的一部分以形成第二导电类型的第二栅极。进行源极/漏极注入以在第二栅极的相对侧上形成第一导电类型的源极区域和漏极区域。源极和漏极区域连接到沟道区域，并且与沟道区域和第一栅极重叠。

10. 发明申请

US20120104387A1 Four-Terminal Metal-Over-Metal Capacitor Design Kit 有权
标题翻译：四端子金属金属电容器设计套件
公开(公告)号：US20120104387A1
公开(公告)日：2012-05-03
申请号：US12915757
申请日：2010-10-29
申请人： Chia-Chung Chen , Chi-Feng Huang , Tse-Hua Lu , Sally Liu
发明人： Chia-Chung Chen , Chi-Feng Huang , Tse-Hua Lu , Sally Liu
IPC分类号： H01L23/544 , H01L29/92
CPC分类号： H01L23/5223 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A device includes a first MOM capacitor; a second MOM capacitor directly over and vertically overlapping the first MOM capacitor, wherein each of the first and the second MOM capacitors includes a plurality of parallel capacitor fingers; a first and a second port electrically coupled to the first MOM capacitor; and a third and a fourth port electrically coupled to the second MOM capacitor. The first, the second, the third, and the fourth ports are disposed at a surface of a respective wafer.
摘要翻译：一种器件包括第一MOM电容器; 第二MOM电容器直接在第一MOM电容器上方并垂直重叠，其中第一和第二MOM电容器中的每一个包括多个并联电容指; 电耦合到第一MOM电容器的第一和第二端口; 以及电耦合到第二MOM电容器的第三和第四端口。第一，第二，第三和第四端口设置在相应晶片的表面。

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