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1. 发明申请

US20090233410A1 Self-Aligned Halo/Pocket Implantation for Reducing Leakage and Source/Drain Resistance in MOS Devices 有权
标题翻译：用于降低MOS器件泄漏和源极/漏极电阻的自对准光晕/口袋植入
公开(公告)号：US20090233410A1
公开(公告)日：2009-09-17
申请号：US12048119
申请日：2008-03-13
申请人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
发明人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26586 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.
摘要翻译：一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质，其中所述半导体衬底和所述栅极电介质的侧壁具有接合点; 在所述栅极电介质上形成栅电极; 在所述半导体衬底和所述栅极电极上形成掩模层，其中所述掩模层的与所述接合点相邻的第一部分至少比所述掩模层的离开所述接合点的第二部分更薄; 在形成掩模层的步骤之后，进行晕/穴注入以将卤素/杂质杂质引入到半导体衬底中; 并且在光晕/口袋植入之后去除掩模层。

2. 发明授权

US08822293B2 Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices 有权
标题翻译：自对准晕圈/凹穴注入，用于减少MOS器件中的漏电和源极/漏极电阻
公开(公告)号：US08822293B2
公开(公告)日：2014-09-02
申请号：US12048119
申请日：2008-03-13
申请人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
发明人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265 , H01L29/66 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/26586 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.
摘要翻译：一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质，其中所述半导体衬底和所述栅极电介质的侧壁具有接合点; 在所述栅极电介质上形成栅电极; 在所述半导体衬底和所述栅极电极上形成掩模层，其中所述掩模层的与所述接合点相邻的第一部分至少比所述掩模层的离开所述接合点的第二部分更薄; 在形成掩模层的步骤之后，进行晕/穴注入以将卤素/杂质杂质引入到半导体衬底中; 并且在光晕/口袋植入之后去除掩模层。

3. 发明授权

US07611963B1 Method for forming a multi-layer shallow trench isolation structure in a semiconductor device 有权
标题翻译：在半导体器件中形成多层浅沟槽隔离结构的方法
公开(公告)号：US07611963B1
公开(公告)日：2009-11-03
申请号：US12111355
申请日：2008-04-29
申请人： Shu-Tine Yang , Chen-Hua Yu , Chu-Yun Fu
发明人： Shu-Tine Yang , Chen-Hua Yu , Chu-Yun Fu
IPC分类号： H01L21/301
CPC分类号： H01L21/76224
摘要： A method for forming a multi-layer shallow trench isolation structure in a semiconductor device is described. In one embodiment, the method includes etching a shallow trench in a silicon substrate of a semiconductor device and forming a dielectric liner layer on a floor and walls of the shallow trench. The method further includes forming a first doped oxide layer in the shallow trench, the first layer formed by vapor deposition of precursors including a source of silicon, a source of oxygen, and sources of doping materials at a first processing condition and forming a second doped oxide layer above the first doped oxide layer by vapor deposition using precursors of silicon and doping materials, at a second processing condition, different from the first processing condition.
摘要翻译：描述了在半导体器件中形成多层浅沟槽隔离结构的方法。在一个实施例中，该方法包括蚀刻半导体器件的硅衬底中的浅沟槽，并在浅沟槽的地板和壁上形成介电衬垫层。该方法还包括在浅沟槽中形成第一掺杂氧化物层，第一层通过在第一处理条件下气相沉积包括硅源，氧源和掺杂源的前体形成，并形成第二掺杂氧化物层，其通过使用硅和掺杂材料的前体的气相沉积，在与第一处理条件不同的第二处理条件下进行。

4. 发明申请

US20090267176A1 A METHOD FOR FORMING A MULTI-LAYER SHALLOW TRENCH ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE 有权
标题翻译：一种在半导体器件中形成多层薄壁分离结构的方法
公开(公告)号：US20090267176A1
公开(公告)日：2009-10-29
申请号：US12111355
申请日：2008-04-29
申请人： Shu-Tine Yang , Chen-Hua Yu , Chu-Yun Fu
发明人： Shu-Tine Yang , Chen-Hua Yu , Chu-Yun Fu
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76224
摘要： The disclosure describes a multi-layer shallow trench isolation structure in a semiconductor device. The shallow trench isolation structure may include a first void-free, doped oxide layer in the shallow trench, and a second void-free layer above the first doped oxide layer. The first layer may be formed by vapor deposition of precursors of a source of silicon, a source of oxygen and sources of doping materials and making the layer void-free by reflowing the initial layer by an annealing process. The second layer may be formed by vapor deposition of precursors of silicon and doping materials and making the layer void-free by reflowing the initial layer by an annealing process. Alternatively, the second layer may be a silicon oxide layer that may be formed by an atomic layer deposition method. The processing conditions for forming the two layers are different.
摘要翻译：本公开描述了半导体器件中的多层浅沟槽隔离结构。浅沟槽隔离结构可以包括浅沟槽中的第一无空隙掺杂氧化物层，以及在第一掺杂氧化物层上方的第二无空隙层。第一层可以通过气相沉积硅源，氧源和掺杂材料的前体而形成，并通过退火工艺回流初始层使层无空隙。可以通过汽相沉积硅和掺杂材料的前体形成第二层，并通过退火工艺回流初始层使层无空隙。或者，第二层可以是可以通过原子层沉积法形成的氧化硅层。用于形成两层的加工条件不同。

5. 发明授权

US08440517B2 FinFET and method of fabricating the same 有权
标题翻译： FinFET及其制造方法
公开(公告)号：US08440517B2
公开(公告)日：2013-05-14
申请号：US12903712
申请日：2010-10-13
申请人： Hung-Ta Lin , Chu-Yun Fu , Shin-Yeh Huang , Shu-Tine Yang , Hung-Ming Chen
发明人： Hung-Ta Lin , Chu-Yun Fu , Shin-Yeh Huang , Shu-Tine Yang , Hung-Ming Chen
IPC分类号： H01L21/02
CPC分类号： H01L27/0886 , H01L21/02293 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7842 , H01L29/7848 , H01L29/785 , H01L29/7855
摘要： The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces; a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin comprises a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin comprises a non-recessed portion having a top surface higher than the tapered top surfaces; and a gate stack over the non-recessed portion of the fin.
摘要翻译：本发明涉及鳍状场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括顶表面的衬底; 第一绝缘区域和位于衬底顶表面上的第二绝缘区域，包括锥形顶表面; 在所述第一和第二绝缘区域之间延伸到所述衬底顶表面之上的所述衬底的翅片，其中所述鳍片包括具有比所述第一和第二绝缘区域的锥形顶表面低的顶表面的凹陷部分，其中所述鳍片包括非加工部分具有高于锥形顶表面的顶表面; 以及在翅片的非凹陷部分上方的栅极堆叠。

6. 发明授权

US08173503B2 Fabrication of source/drain extensions with ultra-shallow junctions 有权
标题翻译：源极/漏极扩展与超浅结的制造
公开(公告)号：US08173503B2
公开(公告)日：2012-05-08
申请号：US12617955
申请日：2009-11-13
申请人： Yihang Chiu , Chu-Yun Fu
发明人： Yihang Chiu , Chu-Yun Fu
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814
摘要： A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting essentially of indium and antimony to a top portion of the semiconductor substrate adjacent to the gate structure. The method further includes, after the step of performing the PAI, implanting a second element different from the first element into the top portion of the semiconductor substrate. The second element includes a p-type element when the first element includes indium, and includes an n-type element when the first element includes antimony.
摘要翻译：形成集成电路器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极结构; 以及通过将选自由铟和锑组成的组中的第一元素注入到与栅极结构相邻的半导体衬底的顶部部分来执行预非晶化注入（PAI）。该方法还包括在执行PAI的步骤之后，将不同于第一元件的第二元件注入到半导体衬底的顶部。当第一元素包括铟时，第二元素包括p型元素，并且当第一元素包括锑时包括n型元素。

7. 发明申请

US20100216288A1 Fabrication of Source/Drain Extensions with Ultra-Shallow Junctions 有权
标题翻译：用超浅接头制造源/排水扩展
公开(公告)号：US20100216288A1
公开(公告)日：2010-08-26
申请号：US12617955
申请日：2009-11-13
申请人： Yihang Chiu , Chu-Yun Fu
发明人： Yihang Chiu , Chu-Yun Fu
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814
摘要： A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting essentially of indium and antimony to a top portion of the semiconductor substrate adjacent to the gate structure. The method further includes, after the step of performing the PAI, implanting a second element different from the first element into the top portion of the semiconductor substrate. The second element includes a p-type element when the first element includes indium, and includes an n-type element when the first element includes antimony.
摘要翻译：形成集成电路器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极结构; 以及通过将选自由铟和锑组成的组中的第一元素注入到与栅极结构相邻的半导体衬底的顶部部分来执行预非晶化注入（PAI）。该方法还包括在执行PAI的步骤之后，将不同于第一元件的第二元件注入到半导体衬底的顶部。当第一元素包括铟时，第二元素包括p型元素，并且当第一元素包括锑时包括n型元素。

8. 发明授权

US08110890B2 Method of fabricating semiconductor device isolation structure 有权
标题翻译：制造半导体器件隔离结构的方法
公开(公告)号：US08110890B2
公开(公告)日：2012-02-07
申请号：US11758043
申请日：2007-06-05
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
IPC分类号： H01L21/70
CPC分类号： H01L21/76202 , H01L21/26506 , H01L21/26533 , H01L21/26586 , H01L21/266 , H01L21/324 , H01L21/762 , H01L21/823481 , H01L29/0649 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
摘要翻译：包括可折入隔离结构的半导体器件和用于制造这种器件的方法。优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。

9. 发明申请

US20080194087A1 Polysilicon gate formation by in-situ doping 有权
公开(公告)号：US20080194087A1
公开(公告)日：2008-08-14
申请号：US11729009
申请日：2007-03-28
申请人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
发明人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
IPC分类号： H01L21/3205 , H01L21/22 , H01L21/38
CPC分类号： H01L29/7834 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

10. 发明申请

US20080194072A1 Polysilicon gate formation by in-situ doping 审中-公开
标题翻译：通过原位掺杂形成多晶硅栅
公开(公告)号：US20080194072A1
公开(公告)日：2008-08-14
申请号：US11705655
申请日：2007-02-12
申请人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
发明人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
IPC分类号： H01L21/336
CPC分类号： H01L21/82345 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.
摘要翻译：一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成第一含硅层，其中所述第一含硅层基本上不含p型和n型杂质; 在所述第一含硅层上形成第二含硅层，其中所述第二含硅层包含杂质; 并进行退火以将第二含硅层中的杂质扩散到第一含硅层中。

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