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1. 发明授权

US08173503B2 Fabrication of source/drain extensions with ultra-shallow junctions 有权
标题翻译：源极/漏极扩展与超浅结的制造
公开(公告)号：US08173503B2
公开(公告)日：2012-05-08
申请号：US12617955
申请日：2009-11-13
申请人： Yihang Chiu , Chu-Yun Fu
发明人： Yihang Chiu , Chu-Yun Fu
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814
摘要： A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting essentially of indium and antimony to a top portion of the semiconductor substrate adjacent to the gate structure. The method further includes, after the step of performing the PAI, implanting a second element different from the first element into the top portion of the semiconductor substrate. The second element includes a p-type element when the first element includes indium, and includes an n-type element when the first element includes antimony.
摘要翻译：形成集成电路器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极结构; 以及通过将选自由铟和锑组成的组中的第一元素注入到与栅极结构相邻的半导体衬底的顶部部分来执行预非晶化注入（PAI）。该方法还包括在执行PAI的步骤之后，将不同于第一元件的第二元件注入到半导体衬底的顶部。当第一元素包括铟时，第二元素包括p型元素，并且当第一元素包括锑时包括n型元素。

2. 发明申请

US20090233410A1 Self-Aligned Halo/Pocket Implantation for Reducing Leakage and Source/Drain Resistance in MOS Devices 有权
标题翻译：用于降低MOS器件泄漏和源极/漏极电阻的自对准光晕/口袋植入
公开(公告)号：US20090233410A1
公开(公告)日：2009-09-17
申请号：US12048119
申请日：2008-03-13
申请人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
发明人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26586 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.
摘要翻译：一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质，其中所述半导体衬底和所述栅极电介质的侧壁具有接合点; 在所述栅极电介质上形成栅电极; 在所述半导体衬底和所述栅极电极上形成掩模层，其中所述掩模层的与所述接合点相邻的第一部分至少比所述掩模层的离开所述接合点的第二部分更薄; 在形成掩模层的步骤之后，进行晕/穴注入以将卤素/杂质杂质引入到半导体衬底中; 并且在光晕/口袋植入之后去除掩模层。

3. 发明授权

US08822293B2 Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices 有权
标题翻译：自对准晕圈/凹穴注入，用于减少MOS器件中的漏电和源极/漏极电阻
公开(公告)号：US08822293B2
公开(公告)日：2014-09-02
申请号：US12048119
申请日：2008-03-13
申请人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
发明人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265 , H01L29/66 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/26586 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.
摘要翻译：一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质，其中所述半导体衬底和所述栅极电介质的侧壁具有接合点; 在所述栅极电介质上形成栅电极; 在所述半导体衬底和所述栅极电极上形成掩模层，其中所述掩模层的与所述接合点相邻的第一部分至少比所述掩模层的离开所述接合点的第二部分更薄; 在形成掩模层的步骤之后，进行晕/穴注入以将卤素/杂质杂质引入到半导体衬底中; 并且在光晕/口袋植入之后去除掩模层。

4. 发明申请

US20100216288A1 Fabrication of Source/Drain Extensions with Ultra-Shallow Junctions 有权
标题翻译：用超浅接头制造源/排水扩展
公开(公告)号：US20100216288A1
公开(公告)日：2010-08-26
申请号：US12617955
申请日：2009-11-13
申请人： Yihang Chiu , Chu-Yun Fu
发明人： Yihang Chiu , Chu-Yun Fu
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814
摘要： A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting essentially of indium and antimony to a top portion of the semiconductor substrate adjacent to the gate structure. The method further includes, after the step of performing the PAI, implanting a second element different from the first element into the top portion of the semiconductor substrate. The second element includes a p-type element when the first element includes indium, and includes an n-type element when the first element includes antimony.
摘要翻译：形成集成电路器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极结构; 以及通过将选自由铟和锑组成的组中的第一元素注入到与栅极结构相邻的半导体衬底的顶部部分来执行预非晶化注入（PAI）。该方法还包括在执行PAI的步骤之后，将不同于第一元件的第二元件注入到半导体衬底的顶部。当第一元素包括铟时，第二元素包括p型元素，并且当第一元素包括锑时包括n型元素。

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