专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08692526B2 Converting leakage current to DC output 有权
标题翻译：将漏电流转换为直流输出
公开(公告)号：US08692526B2
公开(公告)日：2014-04-08
申请号：US12958254
申请日：2010-12-01
申请人： Chee K. Fong , Suet F. Tin , Perry S. Stultz
发明人： Chee K. Fong , Suet F. Tin , Perry S. Stultz
IPC分类号： H02M3/335
CPC分类号： H02M3/33546 , H02M3/33561
摘要： A power source capable of supplying power to operate electronics of a system is disclosed. In one example, the power source takes advantage of an electrical potential difference between primary and secondary grounds. The power source can reduce system cost and power consumption.
摘要翻译：公开了一种能够供电来操作系统的电子设备的电源。在一个示例中，电源利用了初级和次级接地之间的电位差。电源可以降低系统成本和功耗。

2. 发明申请

US20120140527A1 CONVERTING LEAKAGE CURRENT TO DC OUTPUT 有权
标题翻译：将漏电流转换为直流输出
公开(公告)号：US20120140527A1
公开(公告)日：2012-06-07
申请号：US12958254
申请日：2010-12-01
申请人： Chee K. Fong , Suet F. Tin , Perry S. Stultz
发明人： Chee K. Fong , Suet F. Tin , Perry S. Stultz
IPC分类号： H02M3/335
CPC分类号： H02M3/33546 , H02M3/33561
摘要： A power source capable of supplying power to operate electronics of a system is disclosed. In one example, the power source takes advantage of an electrical potential difference between primary and secondary grounds. The power source can reduce system cost and power consumption.
摘要翻译：公开了一种能够供电来操作系统的电子设备的电源。在一个示例中，电源利用了初级和次级接地之间的电位差。电源可以降低系统成本和功耗。

3. 发明授权

US5089957A RAM based events counter apparatus and method 失效
标题翻译：基于RAM的事件计数器和方法
公开(公告)号：US5089957A
公开(公告)日：1992-02-18
申请号：US436212
申请日：1989-11-14
申请人： Perry S. Stultz , James R. Hamstra
发明人： Perry S. Stultz , James R. Hamstra
IPC分类号： G06F11/34 , H03K21/00
CPC分类号： H03K21/00 , G06F11/3409 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A system, for counting the occurrence of a plurality of system events and for prioritizing the order in which count values are to be incremented, receives a plurality of data signals (15) where each signal is associated with a system event. The data signals (15) are stored in a storage register (16). A memory device (12) stores a plurality of count values, where one count value is associated with each system event to be counted. Each count value is stored in a preselected memory location. The storage register (16) also receives a feedback signal (32) to update the signals (15) stored in the register (16). The storage register (16) generates a plurality of signals (19) which are input to a priority decoder (14) and the priority decoder (14) generates a priority signal (32) to address the location in the memory device (12) where the count value to be accessed is stored. The addressed count value (62) is input to an incrementor (22) where it is incremented and the incremented count value is stored in the memory device (12). The system may also include a multiplexer (90) to select the address signal (92) used to address the memory device (12), and temporary storage devices (80, 100) for respectively storing the selected address signal (92) or the count value accessed (62).

4. 发明授权

US06456676B1 Clock signal distribution and synchronization 失效
标题翻译：时钟信号分配和同步
公开(公告)号：US06456676B1
公开(公告)日：2002-09-24
申请号：US09385216
申请日：1999-08-27
申请人： R. Brendan O'Connor , Perry S. Stultz , George N. Bailey, III
发明人： R. Brendan O'Connor , Perry S. Stultz , George N. Bailey, III
IPC分类号： H04L700
CPC分类号： H03L7/14 , G06F1/10 , H03L7/07 , H04L7/0008
摘要： Methods and apparatuses for clock signal distribution and synchronization are described. A base clock signal (e.g., system clock signal) is provided to multiple components of an electronic system. Two or more of the components include clock generation circuitry to generate component clock signals based on the base clock signal. The component clock signals are distributed to one or more other components within the electronic system. The component clock generation circuitry is allowed to synchronize to the base clock signal during a first predetermined period of time (e.g., system boot up). At the end of the first predetermined period of time, the base clock signal is blocked from the component clock generation circuitry for a second predetermined period of time. At the expiration of the second predetermined period of time, the component clock generation circuitry is allowed to re-synchronize with the base clock signal. Because multiple synchronizations are started at the same time, the resulting component clock signals are synchronized to the base clock signal and are in phase with each other (i.e., have a common phase).
摘要翻译：描述了用于时钟信号分配和同步的方法和装置。基本时钟信号（例如，系统时钟信号）被提供给电子系统的多个组件。两个或多个组件包括基于基本时钟信号产生组件时钟信号的时钟产生电路。组件时钟信号被分配到电子系统内的一个或多个其他组件。允许组件时钟产生电路在第一预定时间段（例如，系统启动）期间与基本时钟信号同步。在第一预定时间段结束时，基本时钟信号在组件时钟产生电路中被阻止第二预定时间段。在第二预定时间段期满时，允许组件时钟产生电路与基本时钟信号重新同步。由于同时启动多个同步，所得到的组件时钟信号与基本时钟信号同步并且彼此同相（即具有公共相位）。

5. 发明授权

US5051986A Asynchronous priority select logic 失效
标题翻译：异步优先级选择逻辑
公开(公告)号：US5051986A
公开(公告)日：1991-09-24
申请号：US444628
申请日：1989-12-01
申请人： Robert M. Grow , Perry S. Stultz
发明人： Robert M. Grow , Perry S. Stultz
IPC分类号： G06F15/16 , G06F9/52 , G06F15/173 , G06F15/177 , H04L12/433
CPC分类号： H04L12/433
摘要： The present invention provides asynchronous priority select logic for allowinig an individual station on a token ring network to hold a token for asynchronous transmission only for a specified maximum time period. The asynchronous priority select logic comprises a token rotation timer for timing token rotations on the ring from arrival to arrival. A token holding timer limits the amount of ring bandwidth used by the station for asynchronous transmission after the token is captured by the station. Select circuitry responsive to the value of the token rotation timer determines if the captured token is still usable for transmission by determining if the token rotation timer value is less than a preselected asynchronous threshold value. The select logic includes means for generating a selected asynchronous threshold value having a first bit length. The selected asynchronous threshold value is then expanded to a second bit length corresponding to the bit length of the token holding timer value. The expanded asynchronous threshold value and the token holding timer value are then compared and an output signal is asserted if the expanded selected asynchronous threshold value is greater than the token holding timer value.

6. 发明授权

US5235593A Ring latency timer 失效
标题翻译：环形延迟定时器
公开(公告)号：US5235593A
公开(公告)日：1993-08-10
申请号：US944795
申请日：1992-09-14
申请人： Robert M. Grow , Randall F. Wetzel , Perry S. Stultz
发明人： Robert M. Grow , Randall F. Wetzel , Perry S. Stultz
IPC分类号： H04L12/433
CPC分类号： H04L12/433
摘要： A ring latency timer provides a station attached to a token ring network with the capability of obtaining an accurate latency measurement of the ring to which it is attached. An internal hardware register, which may be read via the processor control bus interface, contains the latest ring latency measurement. A latency interrupt bit, when cleared, enables the latency measurement function. A subsequent interrupt which causes the latency interrupt bit to be set by the chip signals the completion of the latency measurement and the function is once again disabled. The latency register holds the latency information until the interrupt bit is cleared by the processor.
摘要翻译：环形延迟定时器提供附接到令牌环网络的站，其具有获得其所附接的环的精确等待时间测量的能力。可以通过处理器控制总线接口读取的内部硬件寄存器包含最新的环形延迟测量。等待时间中断位清零时，使能延时测量功能。随后的中断使得等待时间中断位由芯片设置，信号延迟测量结束，该功能再次被禁止。延迟寄存器保存延迟信息，直到处理器清除中断位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式