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1. 发明授权

US5577206A System for physical layer controllers for performing automatic hardware based scrubbing of input and output dirty flags for updating system configuration changes 失效
标题翻译：用于物理层控制器的系统，用于执行自动基于硬件的擦除输入和输出脏标志，以更新系统配置更改
公开(公告)号：US5577206A
公开(公告)日：1996-11-19
申请号：US28342
申请日：1993-03-09
申请人： Walter R. Friedrich , James R. Hamstra , James F. Torgerson
发明人： Walter R. Friedrich , James R. Hamstra , James F. Torgerson
IPC分类号： G06F13/38 , G06F13/00
CPC分类号： G06F13/385
摘要： A physical layer controller for use in a data transmission network is disclosed which includes an automatic scrubbing arrangement that is activated upon the occurrence of a physical layer controller reconfiguration. The transmitter output port as well as each channel output of the physical layer controller has an output dirty flag associated therewith. Similarly, the input port as well as each channel input has an associated input dirty flag. A scrubbing arrangement automatically scrubs certain outputs after a configuration change. More specifically, in the absence of a blocking condition after a configuration change, the scrubbing arrangement will automatically scrub each output which has a new source and one of: 1) its associated output dirty flag is set to a first level; and 2) it is connected to an new source which has its associated input dirty flag set to a first level. In a method aspect, output dirty flags are set for each output that has the potential to transmits a data frame. Outputs which have data frame detection available are considered to have the potential to transmit a data frame only when they sense a frame start. Outputs that do not have data frame detection available, are considered to have the potential of having transmitted a data frame anytime they are enabled and coupled to a valid input. The input dirty flags are set for each input that is connected to an output for which the output dirty flag is set.
摘要翻译：公开了一种用于数据传输网络的物理层控制器，其包括在出现物理层控制器重新配置时被激活的自动洗涤装置。发射机输出端口以及物理层控制器的每个通道输出具有与其相关联的输出脏标志。类似地，输入端口以及每个通道输入都具有相关的输入脏标志。擦洗布置会在配置更改后自动擦除某些输出。更具体地，在配置改变之后没有阻塞条件的情况下，洗涤装置将自动擦除具有新源的每个输出和以下之一：1）其相关联的输出脏标志被设置为第一级; 和2）它连接到一个新的源，它的相关输入脏标志设置为第一级。在方法方面，为具有发送数据帧的可能性的每个输出设置输出脏标志。具有可用数据帧检测的输出被认为具有仅在感测到帧起始时才发送数据帧的潜力。没有数据帧检测可用的输出被认为具有发送数据帧的潜力，只要它们被启用并且耦合到有效的输入。为连接到输出脏标志设置的输出的每个输入设置输入脏标志。

2. 发明授权

US5016221A First-in, first-out (FIFO) memory with variable commit point 失效
标题翻译：具有可变提交点的先进先出（FIFO）存储器
公开(公告)号：US5016221A
公开(公告)日：1991-05-14
申请号：US444741
申请日：1989-12-01
申请人： James R. Hamstra
发明人： James R. Hamstra
IPC分类号： G06F5/10 , G06F13/12 , G11C7/00 , H04L13/08
CPC分类号： G06F5/10 , G06F13/128 , G06F2205/108
摘要： A first-in, first-out (FIFO) memory configuration comprising a fully addressable memory (e.g. random access memory), a write pointer, a read pointer, and a third, "commit" pointer serving as a boundary between first and second subsets of data stored within the FIFO. During data reception, a comparator circuit compares a predetermined subset of imcoming data with a predefined reference data set for determining whether the incoming data should be stored or aborted. This determination establishes the appropriate memory address value for positioning the commit pointer. The first subset of data behind the commit pointer may selectively be stored, while the second subset of data ahead of the commit pointer may selectively be aborted. During data transmission, a status register monitors the readiness of the data medium onto which the data is to be transmitted. If and/or when the data medium is ready to accept data, the commit pointer may be selectively positioned to demarcate data committed for transmission.

3. 发明授权

US4873630A Scientific processor to support a host processor referencing common memory 失效
标题翻译：科学处理器支持主机处理器引用通用内存
公开(公告)号：US4873630A
公开(公告)日：1989-10-10
申请号：US761201
申请日：1985-07-31
申请人： John T. Rusterholz , Archie E. Lahti , Louis B. Bushard , Larry L. Byers , James R. Hamstra , Charles J. Homan
发明人： John T. Rusterholz , Archie E. Lahti , Louis B. Bushard , Larry L. Byers , James R. Hamstra , Charles J. Homan
IPC分类号： F02B75/02 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/30018 , G06F9/30036 , G06F9/30065 , G06F9/325 , F02B2075/025
摘要： An improved Scientific Processor for use in a data processing system having a general purpose host processor and a High Performance Storage Unit, and under operational control of the host processor is described. The Scientific Processor includes a Vector Processor Module and a Scalar Processor Module, each operable at comparable rates, wherein scalar operands and vector operands can be manipulated in various combinations under program control of an associated host processor, all without requirement of dedicated storage or caching. The Scalar Processor Module includes instruction flow control circuitry, loop control circuitry for controlling nested loops, and addressing circuitry for generating addresses to be referenced in the High Performance Storage Unit. A scalar processor arithmetic logic unit is described for performing scalar manipulations. The Vector Processor Module includes vector control circuitry and vector file storage circuitry together with vector file loading and vector storage circuitry. A plurality of vector manipulating pipelines for performing instruction functions of vector addition, vector multiplication and vector move is described wherein the pipelined functions can occur simultaneously, and each pipeline is capable of providing resultant operand pairs at a rate approximately equal to the reference cycle of the High Performance Storage Unit.
摘要翻译：描述了一种用于具有通用主机处理器和高性能存储单元的数据处理系统的改进的科学处理器，并且在主处理器的操作控制下。科学处理器包括一个矢量处理器模块和一个标量处理器模块，每个处理器模块以可比较的速率运行，其中标量操作数和矢量操作数可以在相关主机处理器的程序控制下以不同的组合进行操作，而不需要专门的存储或缓存。标量处理器模块包括指令流控制电路，用于控制嵌套循环的环路控制电路，以及用于生成要在高性能存储单元中引用的地址的寻址电路。描述了用于执行标量操作的标量处理器算术逻辑单元。矢量处理器模块包括矢量控制电路和矢量文件存储电路以及矢量文件加载和矢量存储电路。描述了用于执行向量相加，向量乘法和向量移动的指令功能的多个向量操纵流水线，其中流水线函数可以同时发生，并且每个流水线能够以大约等于高性能存储单元。

4. 发明授权

US4811203A Hierarchial memory system with separate criteria for replacement and writeback without replacement 失效
标题翻译：分层存储系统，具有单独的替换和回写标准，无需更换
公开(公告)号：US4811203A
公开(公告)日：1989-03-07
申请号：US354558
申请日：1982-03-03
申请人： James R. Hamstra
发明人： James R. Hamstra
IPC分类号： G06F12/08 , G06F12/12 , G06F13/12
CPC分类号： G06F12/123 , G06F12/0804
摘要： In a memory system having a cache memory and a bulk memory, write-back of data segments in the cache memory to the bulk memory for replacement purposes is accomplished in accordance with a least recently used algorithm while the write-back of written-to segments to the bulk memory without replacement is accomplished in accordance with an age since first write algorithm.
摘要翻译：在具有高速缓冲存储器和大容量存储器的存储器系统中，根据最近最少使用的算法，在写入段的写入期间，完成将高速缓冲存储器中的数据段向大容量存储器进行替换的替换到没有替换的大容量存储器是根据从第一次写入算法的年龄来完成的。

5. 发明授权

US07589978B1 Air inlet diffuser 失效
标题翻译：进气歧管
公开(公告)号：US07589978B1
公开(公告)日：2009-09-15
申请号：US11280784
申请日：2005-11-16
申请人： Paul Holdredge , James R. Hamstra
发明人： Paul Holdredge , James R. Hamstra
IPC分类号： H05K9/00
CPC分类号： H05K7/20145
摘要： An air inlet diffuser 10 is disclosed for attachment relative to an air inlet opening 106 of an electronics enclosure 100. The diffuser 10 extends into the electronics enclosure 100 and provides an increased surface area through which EMI attenuating apertures may be formed. The diffuser 10 also reduces the amount of structure that is disposed within the air inlet opening 106 thereby reducing impedance to airflow through the opening 106 into the enclosure 100. The increased surface are of the diffuser 10 allows for increasing the number of EMI attenuating apertures that may be utilized for a given inlet opening 106. In one embodiment, the total open area of the EMI apertures is greater than the open area of the air inlet opening. In such an embodiment, the EMI apertures provide low impedance to airflow through the diffuser 10 and increased airflow in conjunction with EMI attenuation may be realized.
摘要翻译：空气入口扩散器10被公开用于相对于电子设备外壳100的空气入口开口106附接。扩散器10延伸到电子设备外壳100中并且提供增加的表面积，通过该面积可以形成EMI衰减孔。扩散器10还减少了设置在空气入口开口106内的结构的量，从而减小了通过开口106进入外壳100的气流的阻抗。扩散器10的增加的表面允许增加EMI衰减孔的数量，可以用于给定的入口开口106.在一个实施例中，EMI孔的总开口面积大于空气入口开口的开口面积。在这样的实施例中，EMI孔径对通过扩散器10的气流提供低阻抗，并且可以实现与EMI衰减一起增加的气流。

6. 发明授权

US5185863A Byte-wide elasticity buffer 失效
标题翻译： BYTE-WIDE ELASTICITY BUFFER
公开(公告)号：US5185863A
公开(公告)日：1993-02-09
申请号：US444619
申请日：1989-12-01
申请人： James R. Hamstra , Ronald S. Perloff , Louise Y. Yeung
发明人： James R. Hamstra , Ronald S. Perloff , Louise Y. Yeung
IPC分类号： G06F5/06 , H04J3/06 , H04L7/00 , H04L7/04 , H04L12/42 , H04L13/08
CPC分类号： H04J3/0632 , H04L12/422
摘要： A network station's elasticity buffer includes a memory core together with write and read pointer logic. The memory core includes a START area and a CONTINUATION area which is a cyclic buffer. Under normal conditions, the read pointer follows the write pointer cyclically in the CONTINUATION area. However, upon detection of a start delimiter or upon station reset, the pointers recenter to the START area. Separate synchronizing logic is provided for each of the two recentering modes to reduce metastability problems caused by asynchronous sampling of data. A delay-by-one mechanism is built into the start delimiter mode synchronization scheme so that, under certain conditions, the read pointer is held in the CONTINUATION area for an additional read so an early sample of the read-start signal by the station's local clock while the read pointer is well behind the write pointer will not drop the last character of the previous frame when that frame is not separated from the next start delimiter by a sufficient interframe gap. A look-ahead-look-current detector insures that the there is not too much initial separation between the write pointer and the read pointer. A delay-GO mechanism is built into the reset mode synchronization scheme to prevent irregular dropping of line state characters when the local byte clock is trapped within the metastability window while clock drift is infinitesimal. The read pointer logic also includes a mechanism for preventing the delay-GO mechanism from creating too much initial separation between the write pointer and the read pointer.

7. 发明授权

US5179664A Symbol-wide elasticity buffer with a read-only section and a read-write section 失效
标题翻译：具有只读部分和阅读部分的符号宽度弹性缓冲区
公开(公告)号：US5179664A
公开(公告)日：1993-01-12
申请号：US338587
申请日：1989-04-14
申请人： Gabriel M. Li , James R. Hamstra
发明人： Gabriel M. Li , James R. Hamstra
IPC分类号： H04L13/08 , H04J3/06 , H04L7/00
CPC分类号： H04J3/0632
摘要： A symbol-wide elasticity buffer for a receive/transmit station within an asynchronous data transmission network provides both for reframing after each packet and for the handling of a continuous line state symbol for a period longer than the allowed packet size. According to one aspect of the invention, the elasticity buffer is divided into a START section and a CONTINUATION section. The buffer's write pointer will not enter the CONTINUATION section until the read pointer is directed to the first of the multiple, sequential registers comprising the START section. The read pointer must sequentially read the START section registers before entering the CONTINUATION section. Once the write pointer or read pointer leaves the START section, it can only reenter the START section upon receipt of a start delimiter signal. When the write pointer or the read pointer reaches the last register in the CONTINUATION section, it is automatically routed back to the first CONTINUATION section register. According to a second aspect of the invention, a repeat flag is associated with the last register in the CONTINUATION section. The repeat flag is set upon receipt of any repeatable control signal. With the Repeat Flag set, the read pointer will reach the final CONTINUATION section register and continue to read the same symbol without causing an overflow or underflow. When a new symbol is received, a CONTINUE signal is generated and the write pointer begins writing to the CONTINUATION section. After a predetermined delay, the read pointer begins reading the first register in the CONTINUATION section and the R-Flag is cleared.

8. 发明授权

US4984251A Method and apparatus for the synchronization of a cascaded multi-channel data transmission 失效
标题翻译：用于级联多通道数据传输同步的方法和装置
公开(公告)号：US4984251A
公开(公告)日：1991-01-08
申请号：US394445
申请日：1989-08-16
申请人： Ronald S. Perloff , James R. Hamstra , Gabriel M. Li , Louise Y. Y. Yeung
发明人： Ronald S. Perloff , James R. Hamstra , Gabriel M. Li , Louise Y. Y. Yeung
IPC分类号： H04J3/06
CPC分类号： H04J3/0632 , H04J3/0608
摘要： A method and apparatus for synchronizing the cascaded, multi-channel transmission of a plurality of data characters is provided. Each sequence of data characters preceded by a start delimiter. Each transmission channel provides transmitted data frames to an associated elasticity buffer. As each channel detects a start delimiter, it asserts a begin-request signal that acknowledges detection of the start delimiter. When all channels have detected a start delimiter, a read-start signal is asserted to simultaneously advance the read pointer of each elasticity buffer. In this manner, each elasticity buffer initiates a sunchronized read for local use or retransmission of the multi-channel data.
摘要翻译：提供了一种用于同步多个数据字符的级联多通道传输的方法和装置。每个序列的数据字符都以起始分隔符前面。每个传输通道将传输的数据帧提供给相关联的弹性缓冲器。当每个通道检测到一个起始分隔符时，它断言一个确认起始分隔符检测的开始请求信号。当所有通道都检测到起始分隔符时，一个读取 - 开始信号被断言，以同时推进每个弹性缓冲器的读取指针。以这种方式，每个弹性缓冲器启动用于本地使用或重发多通道数据的同步读取。

9. 发明申请

US20090323282A1 AIR INLET DIFFUSER 有权
公开(公告)号：US20090323282A1
公开(公告)日：2009-12-31
申请号：US12553412
申请日：2009-09-03
申请人： Paul Holdredge , James R. Hamstra
发明人： Paul Holdredge , James R. Hamstra
IPC分类号： H05K9/00 , H05K7/20
CPC分类号： H05K7/20145
摘要： An air inlet diffuser 10 is disclosed for attachment relative to an air inlet opening 106 of an electronics enclosure 100. The diffuser 10 extends into the electronics enclosure 100 and provides an increased surface area through which EMI attenuating apertures may be formed. The diffuser 10 also reduces the amount of structure that is disposed within the air inlet opening 106 thereby reducing impedance to airflow through the opening 106 into the enclosure 100. The increased surface are of the diffuser 10 allows for increasing the number of EMI attenuating apertures that may be utilized for a given inlet opening 106. In one embodiment, the total open area of the EMI apertures is greater than the open area of the air inlet opening. In such an embodiment, the EMI apertures provide low impedance to airflow through the diffuser 10 and increased airflow in conjunction with EMI attenuation may be realized.
摘要翻译：空气入口扩散器10被公开用于相对于电子设备外壳100的空气入口开口106附接。扩散器10延伸到电子设备外壳100中并且提供增加的表面积，通过该面积可以形成EMI衰减孔。扩散器10还减少了设置在空气入口开口106内的结构的量，从而减小了通过开口106进入外壳100的气流的阻抗。扩散器10的增加的表面允许增加EMI衰减孔的数量，可以用于给定的入口开口106.在一个实施例中，EMI孔的总开口面积大于空气入口开口的开口面积。在这样的实施例中，EMI孔径对通过扩散器10的气流提供低阻抗，并且可以实现与EMI衰减一起增加的气流。

10. 发明授权

US5513320A Transmit data descriptor structure in a media access control/host system interface that implements flexible transmit data descriptor structure unit 失效
标题翻译：在实现灵活的发送数据描述符结构单元的媒体访问控制/主机系统接口中发送数据描述符结构
公开(公告)号：US5513320A
公开(公告)日：1996-04-30
申请号：US521274
申请日：1995-08-30
申请人： Desmond W. Young , James R. Hamstra
发明人： Desmond W. Young , James R. Hamstra
IPC分类号： G06F13/00 , H04L12/433 , H04L12/437 , H04L12/56 , H04L29/10 , G06F13/38 , G06F15/173
CPC分类号： H04L49/9042 , H04L12/433 , H04L12/5693 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9047 , H04L49/9068 , H04L49/9073 , H04L49/9094 , H04L12/437
摘要： An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.
摘要翻译：一种用于在局域网与与附接到网络的站相关联的系统存储器之间传送信息的接口系统。该接口系统包括用于在接口系统和存储器系统之间实现信息传送的总线接口单元。指示模块经由总线接口单元将由接口系统接收的信息从网络传送到存储器系统。请求模块将由接口系统接收的信息从存储器系统经由总线接口单元传送到网络。连接到指示模块和请求模块的状态生成/空间管理模块监视其状态并产生相应的状态信号并且管理存储器系统中的存储空间的分配，用于经由接口在网络和存储器系统之间传送的信息系统。

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