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1. 发明申请

US20130009703A1 BULK-DRIVEN CURRENT-SENSE AMPLIFIER AND OPERATING METHOD THEREOF 有权
标题翻译：大容量驱动电流检测放大器及其工作方法
公开(公告)号：US20130009703A1
公开(公告)日：2013-01-10
申请号：US13178698
申请日：2011-07-08
申请人： Che-Wei WU , Meng-Fan CHANG , Ku-Feng LIN
发明人： Che-Wei WU , Meng-Fan CHANG , Ku-Feng LIN
IPC分类号： H03F3/45
CPC分类号： G11C7/06 , G11C7/062 , G11C13/0002 , G11C13/004 , G11C2013/0042 , G11C2013/0054
摘要： A bulk-driven current-sense amplifier and an amplifier operating method are disclosed. The bulk-driven current-sense amplifier includes a differential amplifier, a first driver, and a second driver. The first driver is coupled to the differential amplifier, and a first node is formed at a connectivity segment of the first driver. The second drive is coupled to the differential amplifier, and a second node is formed at a connectivity segment of the second driver. When a first switch of the first driver and a second switch of the second driver are turned on, the differential amplifier charges the first node and the second node. When the charging is completed, the first node and the second node respectively have a different stabilized potential according to currents separately flowing through a first memory unit of the first driver and a second memory unit of the second drive, and the differential amplifier generates a voltage.
摘要翻译：公开了体驱动电流检测放大器和放大器操作方法。体驱动电流检测放大器包括差分放大器，第一驱动器和第二驱动器。第一驱动器耦合到差分放大器，并且第一节点形成在第一驱动器的连接段处。第二驱动器耦合到差分放大器，并且第二节点形成在第二驱动器的连接段处。当第一驱动器的第一开关和第二驱动器的第二开关导通时，差分放大器对第一节点和第二节点充电。当充电完成时，第一节点和第二节点分别根据分别流过第一驱动器的第一存储器单元的电流和第二驱动器的第二存储器单元分别具有不同的稳定电位，并且差分放大器产生电压。

2. 发明申请

US20120092054A1 Charge pump with low noise and high output current and voltage 有权
标题翻译：电荷泵具有低噪声，高输出电流和电压
公开(公告)号：US20120092054A1
公开(公告)日：2012-04-19
申请号：US12906313
申请日：2010-10-18
申请人： Meng-Fan CHANG , Shin-Jang SHEN , Wan-Ying LU
发明人： Meng-Fan CHANG , Shin-Jang SHEN , Wan-Ying LU
IPC分类号： H03K3/00 , G05F1/10
CPC分类号： H02M3/07
摘要： The present invention discloses a charge pump system with low noise and high output current and voltage, comprising: a four phase clock generator used to generate a first signals group; a serial of delay circuits coupled to said four phase clock generator, wherein each of said delay circuits is coupled to a previous delay circuit relative to each of said delay circuits for delaying a signals group received from said previous delay circuit; a first charge pump circuit coupled to the four phase clock generator and the delay circuits; and an output terminal coupled to the first charge pump circuit; wherein high level of said first signal overlaps two sections of high level of said third signal to generate a first overlapping time and a second overlapping time, and said first overlapping time is not equal to said second overlapping time.
摘要翻译：本发明公开了一种具有低噪声，高输出电流和电压的电荷泵系统，包括：用于产生第一信号组的四相时钟发生器; 耦合到所述四相时钟发生器的一系列延迟电路，其中每个所述延迟电路相对于每个所述延迟电路耦合到先前的延迟电路，用于延迟从所述先前延迟电路接收的信号组; 耦合到四相时钟发生器和延迟电路的第一电荷泵电路; 以及耦合到所述第一电荷泵电路的输出端子; 其中所述第一信号的高电平与所述第三信号的高电平的两个部分重叠以产生第一重叠时间和第二重叠时间，并且所述第一重叠时间不等于所述第二重叠时间。

3. 发明申请

US20140043886A1 SENSING MEMORY ELEMENT LOGIC STATES FROM BIT LINE DISCHARGE RATE THAT VARIES WITH RESISTANCE 有权
标题翻译：传感记忆元件状态来自位线放电率，具有电阻
公开(公告)号：US20140043886A1
公开(公告)日：2014-02-13
申请号：US13570305
申请日：2012-08-09
申请人： Jui-Jen WU , Meng-Fan CHANG
发明人： Jui-Jen WU , Meng-Fan CHANG
IPC分类号： G11C7/10 , G11C7/12 , G11C11/21
CPC分类号： G11C7/12 , G11C7/065 , G11C7/14 , G11C11/419
摘要： A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch.
摘要翻译：数字存储元件具有用于读取存储在位单元中的值的读出电路锁存器。在寻址字线之前，位线是预先充电的。在读取操作期间，位线通过在逻辑状态“0”和“1”处具有不同电阻的位单元存储元件耦合到电源电压。参考位线通过比较电阻值耦合到电源电压，特别是两个逻辑状态下存储元件的高电阻和低电阻之间的电阻。在与电阻值相关的速率下，位线上的电压和参考位线斜坡转向切换阈值。第一行放电到开关阈值电压设置感测电路锁存器。

4. 发明申请

US20110309843A1 Discontinuous Type Layer-ID Detector For 3D-IC And Method of The Same 有权
标题翻译：用于3D-IC的不连续型层ID检测器及其方法
公开(公告)号：US20110309843A1
公开(公告)日：2011-12-22
申请号：US12820953
申请日：2010-06-22
申请人： Ming-Pin CHEN , Meng-Fan CHANG , Wei-Cheng WU
发明人： Ming-Pin CHEN , Meng-Fan CHANG , Wei-Cheng WU
IPC分类号： G01R31/02
CPC分类号： G11C5/02 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565
摘要： A 3D-IC detector for each layer of a stacked device with N layer, includes a dividing-two circuit coupled to a (N−1) signal; a first comparator is coupled to the dividing-two circuit, wherein an input A is coupled to an initial layer number signal, an input B of the first comparator is coupled to an output of the dividing-two circuit; a second comparator is coupled to the initial layer number by an input A of the second comparator, and a num is coupled to an input B of the second comparator; a first Add/sub circuit is coupled to the num via an input A of the first Add/sub circuit, and coupled to the first comparator via an input B of the first Add/sub circuit, to the second comparator via an input +/−signal of the first Add/sub circuit; and a second Add/sub circuit coupled to the first comparator via an input A of the second Add/sub circuit, to the num via an input B of the second Add/sub circuit.
摘要翻译：用于具有N层的堆叠装置的每层的3D-IC检测器包括耦合到（N-1）信号的分二电路; 第一比较器耦合到分二电路，其中输入A耦合到初始层号信号，第一比较器的输入B耦合到分二电路的输出; 第二比较器通过第二比较器的输入端A耦合到初始层号，并且num耦合到第二比较器的输入端B; 第一加法/次电路经由第一加法/次电路的输入端A耦合到num，并且经由第一加法/副电路的输入B耦合到第一比较器，经由输入+ - 第一个Add / sub电路的信号; 以及经由第二加法/子电路的输入A耦合到第一比较器的第二加法/子电路经由第二加法/次电路的输入B耦合到num。

5. 发明申请

US20130148402A1 CONTROL SCHEME FOR 3D MEMORY IC 有权
标题翻译： 3D存储IC控制方案
公开(公告)号：US20130148402A1
公开(公告)日：2013-06-13
申请号：US13524980
申请日：2012-06-15
申请人： Meng-Fan CHANG , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
发明人： Meng-Fan CHANG , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
IPC分类号： G11C5/06
CPC分类号： G11C29/023 , G11C8/08 , G11C11/417 , G11C29/028 , G11C29/04 , G11C29/26 , G11C2029/1202 , G11C2029/1206 , G11C2029/2602
摘要： The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.
摘要翻译：本发明公开了一种包括主芯片和至少一个从芯片的3D存储器IC的控制方案。主芯片包括主存储器核心，第一本地定时器，I / O缓冲器，第一焊盘和第二焊盘。至少一个从芯片与主芯片堆叠。每个从芯片包括从存储器核心，第二本地定时器和第三焊盘。第一TSV耦合到第一焊盘和第三焊盘。逻辑控制电路层包括逻辑控制电路和第四焊盘，逻辑控制电路耦合到第四焊盘。第二TSV耦合到第二焊盘和第四焊盘。

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