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1. 发明授权

US08769173B2 Systems and methods for detecting supported small form-factor pluggable (SFP) devices 有权
标题翻译：用于检测支持的小型可插拔（SFP）设备的系统和方法
公开(公告)号：US08769173B2
公开(公告)日：2014-07-01
申请号：US12904721
申请日：2010-10-14
申请人： Charles S. Cardinell , Roger G. Hathorn , Steven E. Klein , Ashwani Kumar , Daniel W. Sherman
发明人： Charles S. Cardinell , Roger G. Hathorn , Steven E. Klein , Ashwani Kumar , Daniel W. Sherman
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/00 , G06F11/3034 , G06F11/3051 , G06F2213/0008
摘要： Systems and methods for detecting supported small form-factor pluggable (SFP) devices in an adapter are provided. One system includes multiple ports, each port configured to be coupled to a SFP device, a tracking device configured to store data representing a list of supported SFP devices for the adapter, and a processor coupled to each of the plurality of ports and the tracking device. The processor is configured to scan each port at start-up, determine if any of the ports is coupled to a non-supported SFP device, and disable any ports that are coupled to a non-supported SFP device. One method includes scanning each port at start-up, determining if any of the ports is coupled to a non-supported SFP device, and disabling any ports that are coupled to a non-supported SFP device. Also provided are computer storage mediums including computer code for performing the above method.
摘要翻译：提供了用于检测适配器中支持的小型可插拔（SFP）设备的系统和方法。一个系统包括多个端口，每个端口被配置为耦合到SFP设备，跟踪设备被配置为存储表示用于适配器的支持的SFP设备的列表的数据，以及耦合到多个端口中的每个端口的跟踪设备。处理器配置为在启动时扫描每个端口，确定是否有任何端口耦合到不支持的SFP设备，并禁用耦合到不支持SFP设备的任何端口。一种方法包括在启动时扫描每个端口，确定是否有任何端口耦合到不支持的SFP设备，以及禁用耦合到不支持SFP设备的任何端口。还提供了包括用于执行上述方法的计算机代码的计算机存储介质。

2. 发明授权

US08606973B1 Managing monitored conditions in adaptors in a multi-adaptor system 有权
标题翻译：管理多适配器系统中适配器中的监视条件
公开(公告)号：US08606973B1
公开(公告)日：2013-12-10
申请号：US13542569
申请日：2012-07-05
申请人： Charles S. Cardinell , Steven E. Klein , Ashwani Kumar , John N. McCauley , Todd C. Sorenson
发明人： Charles S. Cardinell , Steven E. Klein , Ashwani Kumar , John N. McCauley , Todd C. Sorenson
IPC分类号： G06F13/20
CPC分类号： G06F13/385
摘要： Provided are a method, system, and computer program product for managing monitored conditions in adaptors. An adaptor detects a condition comprising one of a plurality of monitored conditions and determines whether the detected condition is indicated on a recent condition list indicating conditions detected at the adaptors. The adaptor communicates the detected condition to cause the detected condition to be included in the recent condition list available at the adaptors in response to determining that the detected condition is not indicated in the recent condition list. Further, a system receives from one of the adaptors indication of a detected condition comprising one of a plurality of monitored conditions that is not indicated on a recent condition list. The received indicated condition is added to the recent condition list to produce an updated recent condition list. Transmission is caused of the updated recent condition list to the adaptors.
摘要翻译：提供了一种用于管理适配器中监视条件的方法，系统和计算机程序产品。适配器检测包括多个监视条件中的一个的条件，并且确定在最近条件列表中是否指示检测到的条件，指示在适配器处检测到的条件。响应于确定在最近条件列表中未指示检测到的条件，适配器通信检测到的条件以使检测到的条件被包括在适配器可用的最近条件列表中。此外，系统从适配器中的一个接收指示检测到的条件，其包括在最近条件列表上未指示的多个监视条件中的一个。接收到的指示条件被添加到最近条件列表以产生更新的最近条件列表。传输是由适配器更新的最新条件列表引起的。

3. 发明申请

US20120089861A1 INTER-PROCESSOR FAILURE DETECTION AND RECOVERY 有权
标题翻译：处理器故障检测和恢复
公开(公告)号：US20120089861A1
公开(公告)日：2012-04-12
申请号：US12902501
申请日：2010-10-12
申请人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
发明人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/0757 , G06F11/0724
摘要： An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.
摘要翻译：公开了一种在多处理器环境中检测处理器故障的方法。该方法可以包括使系统中的每个CPU负责监视系统中的另一个CPU。 CPUn读取CPUn + 1创建的时间戳+1，CPUn正在从共享内存位置进行监控。 CPUn读取自己的时间戳，并比较两个时间戳来计算增量值。如果增量值高于阈值，CPUn确定CPUn + 1失败，并启动系统中CPU的错误处理。一个CPU可能被指定为主CPU，并负责开始错误处理过程。在这种实施例中，CPUn可以通过通知主CPU CPUn + 1失败来启动错误处理。如果CPUn + 1是主CPU，CPUn可能会采取额外的步骤来启动错误处理，并可能会向所有CPU广播非关键中断，从而触发错误处理。

4. 发明授权

US08904058B2 Selecting direct memory access engines in an adaptor input/output (I/O) requests received at the adaptor 有权
标题翻译：在适配器上接收的适配器输入/输出（I / O）请求中选择直接内存访问引擎
公开(公告)号：US08904058B2
公开(公告)日：2014-12-02
申请号：US13118093
申请日：2011-05-27
申请人： Charles S. Cardinell , Roger G. Hathorn , Matthew J. Kalos , Timothy J. Van Patten
发明人： Charles S. Cardinell , Roger G. Hathorn , Matthew J. Kalos , Timothy J. Van Patten
IPC分类号： G06F13/28 , G06F13/00 , G06F9/50
CPC分类号： G06F13/28 , G06F9/5011 , G06F9/505
摘要： Provided are a computer program product, system, and method for selecting Direct Memory Access (DMA) engines in an adaptor for processing Input/Output requests received at the adaptor. A determination is made of an assignment of a plurality of processors to the DMA engines, wherein each processor is assigned to use one of the DMA engines. I/O request related work for a received I/O request directed to the storage is processed by determining the DMA engine assigned to the processor processing the I/O request related work and accessing the determined DMA engine to perform the I/O related work.
摘要翻译：提供了一种用于在适配器中选择直接存储器访问（DMA）引擎以用于处理在适配器处接收的输入/输出请求的计算机程序产品，系统和方法。确定将多个处理器分配给DMA引擎，其中分配每个处理器以使用DMA引擎之一。通过确定分配给处理器的处理I / O请求相关工作的DMA引擎并访问确定的DMA引擎来执行与I / O相关的工作来处理针对存储器的接收的I / O请求的I / O请求相关工作。

5. 发明授权

US08850262B2 Inter-processor failure detection and recovery 有权
标题翻译：处理器间故障检测和恢复
公开(公告)号：US08850262B2
公开(公告)日：2014-09-30
申请号：US12902501
申请日：2010-10-12
申请人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
发明人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0757 , G06F11/0724
摘要： An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.
摘要翻译：公开了一种在多处理器环境中检测处理器故障的方法。该方法可以包括使系统中的每个CPU负责监视系统中的另一个CPU。 CPUn读取CPUn + 1创建的时间戳+1，CPUn正在从共享内存位置进行监控。 CPUn读取自己的时间戳，并比较两个时间戳来计算增量值。如果增量值高于阈值，CPUn确定CPUn + 1失败，并启动系统中CPU的错误处理。一个CPU可能被指定为主CPU，并负责开始错误处理过程。在这种实施例中，CPUn可以通过通知主CPU CPUn + 1失败来启动错误处理。如果CPUn + 1是主CPU，CPUn可能会采取额外的步骤来启动错误处理，并可能会向所有CPU广播非关键中断，从而触发错误处理。

6. 发明授权

US09075720B2 Locking a cache line for write operations on a bus 有权
标题翻译：在总线上锁定缓存行以进行写操作
公开(公告)号：US09075720B2
公开(公告)日：2015-07-07
申请号：US12897555
申请日：2010-10-04
申请人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
发明人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0879 , G06F12/0802 , G06F12/0804 , G06F12/0833 , G06F12/0891 , G06F12/1009 , G06F12/127 , G06F12/1475 , G06F2212/1052 , G06F2212/303 , G06F2212/604 , G06F2212/62 , G06F2212/657
摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.
摘要翻译：提供了一种用于在总线上锁定用于突发写入操作的高速缓存行的计算机程序产品，系统和方法。在目标地址的缓存中分配高速缓存行。为缓存行设置锁定，其中设置锁定防止高速缓存行中的数据被抛出。数据被写入缓存行。响应于完成对高速缓存线的写入，高速缓存行中的所有数据都通过总线刷新到目标地址。

7. 发明申请

US20120303842A1 SELECTING DIRECT MEMORY ACCESS ENGINES IN AN ADAPTOR FOR PROCESSING INPUT/OUTPUT (I/O) REQUESTS RECEIVED AT THE ADAPTOR 有权
标题翻译：在适配器中选择直接存储器访问引擎，用于处理在适配器中接收的输入/输出（I / O）请求
公开(公告)号：US20120303842A1
公开(公告)日：2012-11-29
申请号：US13118093
申请日：2011-05-27
申请人： Charles S. Cardinell , Roger G. Hathorn , Matthew J. Kalos , Timothy J. Van Patten
发明人： Charles S. Cardinell , Roger G. Hathorn , Matthew J. Kalos , Timothy J. Van Patten
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F9/5011 , G06F9/505
摘要： Provided are a computer program product, system, and method for selecting Direct Memory Access (DMA) engines in an adaptor for processing Input/Output requests received at the adaptor. A determination is made of an assignment of a plurality of processors to the DMA engines, wherein each processor is assigned to use one of the DMA engines. I/O request related work for a received I/O request directed to the storage is processed by determining the DMA engine assigned to the processor processing the I/O request related work and accessing the determined DMA engine to perform the I/O related work.
摘要翻译：提供了一种用于在适配器中选择直接存储器访问（DMA）引擎以用于处理在适配器处接收的输入/输出请求的计算机程序产品，系统和方法。确定将多个处理器分配给DMA引擎，其中分配每个处理器以使用DMA引擎之一。通过确定分配给处理器的处理I / O请求相关工作的DMA引擎并访问确定的DMA引擎来执行与I / O相关的工作来处理针对存储器的接收的I / O请求的I / O请求相关工作。

8. 发明申请

US20120084514A1 LOCKING A CACHE LINE FOR WRITE OPERATIONS ON A BUS 有权
标题翻译：锁定用于在总线上进行写操作的高速缓存线
公开(公告)号：US20120084514A1
公开(公告)日：2012-04-05
申请号：US12897555
申请日：2010-10-04
申请人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
发明人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
IPC分类号： G06F12/08 , G06F13/24 , G06F12/00
CPC分类号： G06F12/0879 , G06F12/0802 , G06F12/0804 , G06F12/0833 , G06F12/0891 , G06F12/1009 , G06F12/127 , G06F12/1475 , G06F2212/1052 , G06F2212/303 , G06F2212/604 , G06F2212/62 , G06F2212/657
摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.
摘要翻译：提供了一种用于在总线上锁定用于突发写入操作的高速缓存行的计算机程序产品，系统和方法。在目标地址的缓存中分配高速缓存行。为缓存行设置锁定，其中设置锁定防止高速缓存行中的数据被抛出。数据被写入缓存行。响应于完成对高速缓存线的写入，高速缓存行中的所有数据都通过总线刷新到目标地址。

9. 发明授权

US08935511B2 Determining processor offsets to synchronize processor time values 有权
标题翻译：确定处理器偏移量以同步处理器时间值
公开(公告)号：US08935511B2
公开(公告)日：2015-01-13
申请号：US12902047
申请日：2010-10-11
申请人： Charles S. Cardinell , Bernhard Laubli , Timothy J. Van Patten
发明人： Charles S. Cardinell , Bernhard Laubli , Timothy J. Van Patten
IPC分类号： G06F1/14 , G06F11/16
CPC分类号： G06F9/30087 , G06F1/12 , G06F1/14 , G06F11/1675
摘要： Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.
摘要翻译：提供了一种用于确定处理器偏移以同步处理器时间值的计算机程序产品，系统和方法。确定主处理器偏离主处理器的多个时间值之一和从属处理器之一的时间值的偏移。确定从处理器偏移，其中从主处理器偏移确定每个从处理器偏移，主处理器的时间值之一和从属处理器的时间值之一。主处理器的当前时间值由主处理器偏移量调整。每个从属处理器的当前时间值由对其时间值正在调整的从属处理器的从属处理器偏移进行调整。

10. 发明申请

US20120089815A1 DETERMINING PROCESSOR OFFSETS TO SYNCHRONIZE PROCESSOR TIME VALUES 有权
标题翻译：确定处理器以同步处理器时间值
公开(公告)号：US20120089815A1
公开(公告)日：2012-04-12
申请号：US12902047
申请日：2010-10-11
申请人： Charles S. Cardinell , Bernhard Laubli , Timothy J. Van Patten
发明人： Charles S. Cardinell , Bernhard Laubli , Timothy J. Van Patten
IPC分类号： G06F15/76
CPC分类号： G06F9/30087 , G06F1/12 , G06F1/14 , G06F11/1675
摘要： Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.
摘要翻译：提供了一种用于确定处理器偏移以同步处理器时间值的计算机程序产品，系统和方法。确定主处理器偏离主处理器的多个时间值之一和从属处理器之一的时间值的偏移。确定从处理器偏移，其中从主处理器偏移确定每个从处理器偏移，主处理器的时间值之一和从属处理器的时间值之一。主处理器的当前时间值由主处理器偏移量调整。每个从属处理器的当前时间值由对其时间值正在调整的从属处理器的从属处理器偏移进行调整。

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