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1. 发明申请

US20080132065A1 METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN 失效
标题翻译：在集成电路设计中从VIAS重新排列无声扩散的方法
公开(公告)号：US20080132065A1
公开(公告)日：2008-06-05
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

2. 发明授权

US07582566B2 Method for redirecting void diffusion away from vias in an integrated circuit design 失效
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法
公开(公告)号：US07582566B2
公开(公告)日：2009-09-01
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/311
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

3. 发明授权

US07023067B2 Bond pad design 失效
标题翻译：焊盘设计
公开(公告)号：US07023067B2
公开(公告)日：2006-04-04
申请号：US10341082
申请日：2003-01-13
申请人： Derryl D. J. Allman , Charles E. May
发明人： Derryl D. J. Allman , Charles E. May
IPC分类号： H01L31/10
CPC分类号： H01L24/05 , H01L24/48 , H01L2224/04042 , H01L2224/05082 , H01L2224/05093 , H01L2224/05095 , H01L2224/05187 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/05647 , H01L2224/4807 , H01L2224/4845 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2224/45099 , H01L2924/00
摘要： A bonding pad for an integrated circuit, where the bonding pad overlies a fragile dielectric layer. A lower metal layer stack overlies the fragile dielectric layer, and a hard dielectric layer overlies the lower metal layer stack. An upper metal layer stack overlies the hard dielectric layer, where the upper metal layer stack forms voids extending into the upper metal layer stack from an exposed upper surface of the upper metal layer stack. The voids define deformable protrusions in the upper surface of the upper metal layer stack, for at least partially absorbing forces applied to the bonding pad during a bonding operation. Electrically conductive vias extend from the lower metal layer stack through the hard dielectric layer to the upper metal layer stack, and electrically connect the lower metal layer stack to the upper metal layer stack.
摘要翻译：一种用于集成电路的焊盘，其中所述焊盘覆盖在脆性介电层上。下部金属层堆叠在脆性介电层之上，并且硬介电层覆盖在下部金属层堆叠上。上部金属层堆叠在硬介电层之上，其中上部金属层堆叠形成从上部金属层堆叠的暴露的上表面延伸到上部金属层堆叠中的空隙。空隙限定上金属层堆叠的上表面中的可变形突起，用于在粘合操作期间至少部分地吸收施加到接合焊盘的力。导电通孔从下金属层堆叠穿过硬介电层延伸到上金属层堆叠，并将下金属层堆叠电连接到上金属层堆叠。

4. 发明授权

US07436040B2 Method and apparatus for diverting void diffusion in integrated circuit conductors 有权
标题翻译：用于在集成电路导体中转移空穴扩散的方法和装置
公开(公告)号：US07436040B2
公开(公告)日：2008-10-14
申请号：US11323398
申请日：2005-12-29
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L23/58
CPC分类号： H01L21/7682 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
摘要翻译：在集成电路中转移空穴扩散的方法包括以下步骤：在集成电路的第一导电层中形成具有边界的电导体，在电介质层的边界内在第一导电层和第二导电层，并且在电导体的通孔和边界之间形成槽，用于将电导体中的空隙扩散转移离开通孔。

5. 发明授权

US07361965B2 Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design 有权
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法和装置
公开(公告)号：US07361965B2
公开(公告)日：2008-04-22
申请号：US11323400
申请日：2005-12-29
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L23/58
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：用于在集成电路设计中将空隙扩散转向远离通孔的方法和装置包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二电导体之间形成通孔集成电路设计的导电层，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

6. 发明授权

US06654226B2 Thermal low k dielectrics 失效
标题翻译：热低k电介质
公开(公告)号：US06654226B2
公开(公告)日：2003-11-25
申请号：US10094520
申请日：2002-03-08
申请人： Charles E. May , Derryl D. J. Allman
发明人： Charles E. May , Derryl D. J. Allman
IPC分类号： H01G406
CPC分类号： H01L21/02129 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/3122 , H01L21/31625 , H01L21/76828
摘要： An integrated circuit having an electrically insulating layer of an electrically nonconductive material, where the electrically insulating layer is disposed between at least two electrically conductive elements. The electrically nonconductive material is selected from a group of materials having a k value that decreases when subjected to thermal treatment. The electrically nonconductive material is most preferably a boro siloxane.
摘要翻译：一种具有非绝缘材料的电绝缘层的集成电路，其中所述电绝缘层设置在至少两个导电元件之间。非导电材料选自具有在经受热处理时降低的k值的材料组。非导电材料最优选为硼硅氧烷。

7. 发明授权

US06583026B1 Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure 有权
标题翻译：在集成电路结构上形成低k碳掺杂氧化硅介电材料的工艺
公开(公告)号：US06583026B1
公开(公告)日：2003-06-24
申请号：US09872058
申请日：2001-05-31
申请人： Derryl D. J. Allman , Ponce Saopraseuth , Hemanshu D. Bhatt
发明人： Derryl D. J. Allman , Ponce Saopraseuth , Hemanshu D. Bhatt
IPC分类号： H01L2176
CPC分类号： H01L21/02126 , C23C16/401 , H01L21/02211 , H01L21/0228 , H01L21/02304 , H01L21/0234 , H01L21/31633
摘要： A process for forming a low k carbon-doped silicon oxide dielectric material (lkc-dsodm) on an integrated circuit structure is characterized by improved planarity and good gap fill in high aspect ratio regions of the integrated circuit structure, as well as improved film strength and adherence, and less byproducts trapped in the film. The process comprises: depositing a plurality of layers of lkc-dsodm on an integrated circuit structure in a reactor; and pausing after depositing each layer of lkc-dsodm and before depositing a further layer of lkc-dsodm. The process can further include first forming a base or barrier layer of a silicon-rich and nitrogen-rich dielectric material over the integrated circuit structure, plasma etching the upper surface of the barrier layer to facilitate adhesion of the subsequently deposited lkc-dsodm to the barrier layer, and then, before depositing the first layer of lkc-dsodm, cooling the etched barrier layer down to within 10° C. or less of the subsequent deposition temperature used for formation of the film of lkc-dsodm. In another aspect of the invention the pausing step further includes, before deposition of the next layer of lkc-dsodm, flowing a source of non-reactive gas over the surface of the newly deposited layer of lkc-dsodm to facilitate outgassing and removal of byproducts resulting from the preceding formation and deposition of lkc-dsodm.
摘要翻译：在集成电路结构上形成低k碳掺杂氧化硅电介质材料（lkc-dsodm）的方法的特征在于集成电路结构的高纵横比区域中的平坦度和良好的间隙填充，以及改进的膜强度和坚持，更少的副产品被困在电影中。该方法包括：在反应器中的集成电路结构上沉积多层lkc-dsodm; 并且在沉积每层lkc-dsodm之后并在沉积另外一层lkc-dsodm之前暂停。该方法还可以包括首先在集成电路结构上形成富硅和富氮介电材料的基底或阻挡层，等离子体蚀刻阻挡层的上表面，以便于随后沉积的lkc-dsodm粘附到然后在沉积第一层lkc-dsodm之前，将蚀刻的阻挡层冷却到用于形成lkc-dsodm膜的后续沉积温度的10℃以内。在本发明的另一方面，暂停步骤还包括在沉积下一层lkc-dsodm之前，将非反应性气体源流过新沉积的lkc-dsodm层的表面以便于除气和除去副产物由于以前的lkc-dsodm的形成和沉积而产生。

8. 发明授权

US06504250B1 Integrated circuit device with reduced cross talk 失效
公开(公告)号：US06504250B1
公开(公告)日：2003-01-07
申请号：US09695598
申请日：2000-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

9. 发明授权

US06504202B1 Interconnect-embedded metal-insulator-metal capacitor 有权
标题翻译：互连嵌入式金属 - 绝缘体 - 金属电容器
公开(公告)号：US06504202B1
公开(公告)日：2003-01-07
申请号：US09496971
申请日：2000-02-02
申请人： Derryl D. J. Allman , Kenneth Fuchs
发明人： Derryl D. J. Allman , Kenneth Fuchs
IPC分类号： H01L2976
CPC分类号： H01L28/40 , H01L21/768 , H01L28/75
摘要： A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.
摘要翻译：金属 - 绝缘体 - 金属电容器嵌入在集成电路（IC）的互连层中。互连层具有空腔，并且电容器形成在空腔中，电容器的一个板与互连层的导电层成一体，因此电容器板与互连层电连通。互连层具有多个导电层，包括在制造IC期间在特定温度下经受变形的诸如铝的层，并且空腔延伸穿过该层。互连层的剩余导电层限定电容器板中的一个，并且在腔内形成介电层和另一电容器板。通过大致相同长度的互连电连接到顶板并且通过互连层连接到底板。

10. 发明授权

US06448653B1 Method for using low dielectric constant material in integrated circuit fabrication 失效
标题翻译：在集成电路制造中使用低介电常数材料的方法
公开(公告)号：US06448653B1
公开(公告)日：2002-09-10
申请号：US09694993
申请日：2000-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.
摘要翻译：通过旋转在半导体芯片的钝化层上施加低电介质材料以填充可能存在于顶层金属线之间的间隙，从而最小化可能存在于这些线之间的串扰的可能性。

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