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    • 2. 发明授权
    • Method to compensate for a fade in a digital video input sequence
    • 补偿数字视频输入序列中的褪色的方法
    • US6040875A
    • 2000-03-21
    • US046290
    • 1998-03-23
    • Charles E. BoiceJohn M. KaczmarczykAgnes Y. NgaiMichael P. Vachon
    • Charles E. BoiceJohn M. KaczmarczykAgnes Y. NgaiMichael P. Vachon
    • H04N5/265H04N7/26H04N7/50H04N9/74H04N5/14H04N7/12
    • H04N5/265
    • A method to compensate for a fade in a digital video input sequence is provided where the video input sequence is to be compressed according to the MPEG-2 video compression standard. The method comprises a first step of dividing each frame of a current frame into two fields. In a second step, each field of the current frame is divided into at least one field band. In a third step, the luminance and chrominance pixel values are individually summed for the pixels in each field of the current frame. In a fourth step, the luminance pixel values are summed for the pixels in each field band of the current frame. In a fifth step, each respective field band sum and field sum of the current frame is compared with that of the previous frame in the video input sequence. In a sixth step, detection of whether or not a fade has occurred is provided, based upon the comparison in the fifth step. In a seventh step, the encoding algorithm is adjusted if a fade has occurred. Lastly, the first through seventh steps are repeated for at least one subsequent frame in the input video sequence.
    • 提供一种补偿数字视频输入序列中的褪色的方法,其中视频输入序列将根据MPEG-2视频压缩标准进行压缩。 该方法包括将当前帧的每帧划分成两个场的第一步骤。 在第二步骤中,当前帧的每个场被划分成至少一个场频带。 在第三步骤中,针对当前帧的每个场中的像素对亮度和色度像素值进行单独相加。 在第四步骤中,针对当前帧的每个场频带中的像素求和亮度像素值。 在第五步骤中,将当前帧的每个相应的场频和和和与视频输入序列中的前一帧的场和进行比较。 在第六步骤中,基于第五步的比较,提供是否发生褪色的检测。 在第七步中,如果发生褪色,则调整编码算法。 最后,对输入视频序列中的至少一个后续帧重复第一至第七步骤。
    • 8. 发明授权
    • Multiple encoder architecture for extended search
    • 用于扩展搜索的多编码器架构
    • US06823013B1
    • 2004-11-23
    • US09046289
    • 1998-03-23
    • Charles E. BoiceJohn A. MurdockAgnes Y. Ngai
    • Charles E. BoiceJohn A. MurdockAgnes Y. Ngai
    • H04B166
    • H04N19/43H04N19/436H04N19/57
    • An apparatus used for video encoding MPEG compliant digital visual images, having multiple MPEG encoders used in the motion estimation function. The search capabilities used in the motion estimation function of a single MPEG encoder are extended beyond its design limitations as a result of utilizing more than one MPEG encoder. The utilization of multiple encoders effectively creates the capability for a user to specify a wider search window than what is available in a single encoder configuration. The computational search efficency associated with searching the wider window is not adversely affected as a consequence of the multiple processors subdividing the extended window and analyzing each subdivision in parallel.
    • 一种用于视频编码MPEG兼容数字视觉图像的装置,具有用于运动估计功能的多个MPEG编码器。 使用单个MPEG编码器的运动估计功能的搜索能力由于使用多于一个的MPEG编码器而超出其设计限制。 多个编码器的利用有效地创建了用户指定比单个编码器配置中可用的更广泛的搜索窗口的能力。 与多个处理器细分扩展窗口并并行分析每个细分的结果,与搜索较宽窗口相关联的计算搜索效率不受不利影响。
    • 9. 发明授权
    • Apparatus and method for testing programmable delays
    • 用于测试可编程延迟的装置和方法
    • US06253333B1
    • 2001-06-26
    • US09046284
    • 1998-03-23
    • Stanley J. BogumilCharles E. BoiceFrederic G. WebsterRobert L. Woodard
    • Stanley J. BogumilCharles E. BoiceFrederic G. WebsterRobert L. Woodard
    • G06F104
    • G01R31/3016
    • Automatic generation of a timed delay for a timing clock signal input to an electronic device having a time critical circuit receiving address, data, and control signals at a first time interval and performing data storage and data output operations at subsequent second time intervals as determined by the timing clock signal input thereto. The time delay is generated by combination of a first control device for determining a timing condition of the time critical circuit in accordance with data output results corresponding to a first data storage operation performed by the time critical circuit; and, a second control circuit for automatically adjusting the input of the timing clock signal in time with respect to the first time interval in accordance with the data output results. Adjustment of the timing clock signal delay for subsequent data storage operations optimizes time critical circuit performance for the electronic device.
    • 自动生成定时时钟信号,该定时时钟信号输入到具有时间关键电路的电子设备,该电子设备具有以第一时间间隔接收地址,数据和控制信号,并在随后的第二时间间隔执行数据存储和数据输出操作, 定时时钟信号输入到其中。 时间延迟通过组合第一控制装置而产生,该第一控制装置根据对应于由时间关键电路执行的第一数据存储操作的数据输出结果来确定时间关键电路的定时状态; 以及第二控制电路,用于根据数据输出结果自动调整定时时钟信号相对于第一时间间隔的时间。 用于后续数据存储操作的定时时钟信号延迟的调整优化了电子设备的时间关键电路性能。