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1. 发明授权

US09334583B2 Method of preventing auto-doping during epitaxial layer growth by cleaning the reaction chamber with hydrogen chloride 有权
标题翻译：通过用氯化氢清洗反应室来防止外延层生长期间的自掺杂的方法
公开(公告)号：US09334583B2
公开(公告)日：2016-05-10
申请号：US13202944
申请日：2011-06-27
申请人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
发明人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
IPC分类号： C30B25/02 , C30B25/18 , C30B29/06 , C30B23/02 , H01L21/02
CPC分类号： C30B25/186 , C30B23/025 , C30B25/02 , C30B29/06 , H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02661
摘要： An epitaxial growth method for preventing auto-doping effect is presented. This method starts with the removal of impurities from the semiconductor substrate and the reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region.
摘要翻译：提出了一种防止自动掺杂效应的外延生长方法。该方法首先从要使用的半导体衬底和反应室中除去杂质。然后，在从半导体衬底的表面脱离的掺杂剂原子的提取之前，将半导体衬底装载在清洁的反应室中，以在真空条件下预烘烤。接下来，在高温低气流条件下，在所述半导体衬底的表面上形成第一本征外延层。接下来，在低温和高气体流动条件下，在生长的本征外延层的结构表面上形成所需厚度的第二外延层。最后，冷却后硅片卸载。该方法可以防止在半导体衬底上的外延生长期间的自掺杂效应，从而确保外围电路区域中器件的性能和可靠性。

2. 发明申请

US20130189799A1 METHOD OF FABRICATING DUAL TRENCH ISOLATED EPITAXIAL DIODE ARRAY 有权
标题翻译：双层分离分离的外延二极体阵列的方法
公开(公告)号：US20130189799A1
公开(公告)日：2013-07-25
申请号：US13203135
申请日：2011-06-23
申请人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
发明人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
IPC分类号： H01L21/762
CPC分类号： H01L21/76205 , H01L21/76224 , H01L27/0814
摘要： The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory.
摘要翻译：本发明公开了一种制造双沟槽隔离外延二极管阵列的方法。该方法开始于在衬底上形成重掺杂的第一导电类型区域和重掺杂的第二导电类型区域，随后进行外延生长，然后通过深沟槽蚀刻形成二极管阵列字线之间的隔离，并形成通过浅沟槽蚀刻垂直于深沟槽的位线之间的隔离，最后通过离子注入由深和浅沟槽隔离所包围的区域中形成分离的二极管阵列单元。本发明还提供了一种防止由前述的双浅沟槽隔离的外延二极管阵列的相邻字线和位线之间的串扰电流的方法。本发明可用于二极管驱动，高密度，大容量存储器，如相变随机存取存储器，电阻存储器，磁存储器和铁电存储器; 其方法与常规的互补金属氧化物半导体（CMOS）工艺完全兼容，并且由于可以在外围电路形成之前形成二极管阵列，所以不会由于其热处理而引起外围电路的漂移，从而解决了制造高密度，大容量嵌入式相变随机存取存储器的技术挑战。

3. 发明授权

US08586405B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08586405B2
公开(公告)日：2013-11-19
申请号：US13369738
申请日：2012-02-09
申请人： Chao Zhang , Guanping Wu , Bo Liu , Zhitang Song
发明人： Chao Zhang , Guanping Wu , Bo Liu , Zhitang Song
IPC分类号： H01L29/02
CPC分类号： H01L27/1021 , H01L21/74 , H01L27/2409 , H01L29/66136 , H01L29/861
摘要： A method of manufacturing a semiconductor device and a semiconductor device made by the method is disclosed. The method comprises forming a buried N+ layer in an upper portion of a P-type substrate; performing ion implantation on the buried N+ layer; annealing the buried N+ layer; forming an epitaxial semiconductor layer on the buried N+ layer through epitaxial deposition, wherein, an upper portion of said epitaxial semiconductor layer and a portion underlying said P+ region of said epitaxial semiconductor layer are doped to form a P+ region and an N− region, respectively. Increasing the ion implant dosage of the BNL layer, adjusting the method of annealing the BNL layer to increase the width of the BNL layer, or increasing the thickness of the EPI layer, reduces the vertical BJT current gain and suppressed the substrate leakage current.
摘要翻译：公开了一种通过该方法制造半导体器件和半导体器件的方法。该方法包括在P型衬底的上部形成掩埋的N +层; 对掩埋的N +层进行离子注入; 退火埋N +层; 通过外延沉积在掩埋的N +层上形成外延半导体层，其中，所述外延半导体层的上部和所述外延半导体层的所述P +区下面的部分被掺杂以分别形成P +区和N区。增加BNL层的离子注入剂量，调整BNL层的退火方法以增加BNL层的宽度或增加EPI层的厚度，减小垂直BJT电流增益并抑制衬底漏电流。

4. 发明授权

US08476085B1 Method of fabricating dual trench isolated epitaxial diode array 有权
标题翻译：制造双沟槽隔离外延二极管阵列的方法
公开(公告)号：US08476085B1
公开(公告)日：2013-07-02
申请号：US13203135
申请日：2011-06-23
申请人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
发明人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
IPC分类号： H01L21/00
CPC分类号： H01L21/76205 , H01L21/76224 , H01L27/0814
摘要： The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory.
摘要翻译：本发明公开了一种制造双沟槽隔离外延二极管阵列的方法。该方法开始于在衬底上形成重掺杂的第一导电类型区域和重掺杂的第二导电类型区域，随后进行外延生长，然后通过深沟槽蚀刻形成二极管阵列字线之间的隔离，并形成通过浅沟槽蚀刻垂直于深沟槽的位线之间的隔离，最后通过离子注入由深和浅沟槽隔离所包围的区域中形成分离的二极管阵列单元。本发明还提供了一种防止由前述的双浅沟槽隔离的外延二极管阵列的相邻字线和位线之间的串扰电流的方法。本发明可用于二极管驱动，高密度，大容量存储器，如相变随机存取存储器，电阻存储器，磁存储器和铁电存储器; 其方法与常规的互补金属氧化物半导体（CMOS）工艺完全兼容，并且由于可以在外围电路形成之前形成二极管阵列，所以不会由于其热处理而引起外围电路的漂移，从而解决了制造高密度，大容量嵌入式相变随机存取存储器的技术挑战。

5. 发明申请

US20130145984A1 METHOD OF EPITAXIAL GROWTH EFFECTIVELY PREVENTING AUTO-DOPING EFFECT 有权
标题翻译：有效防止自动排污效果的外源生长方法
公开(公告)号：US20130145984A1
公开(公告)日：2013-06-13
申请号：US13202944
申请日：2011-06-27
申请人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang
发明人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang
IPC分类号： C30B25/18 , C30B23/02
CPC分类号： C30B25/186 , C30B23/025 , C30B25/02 , C30B29/06 , H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02661
摘要： This invention relates to a method of epitaxial growth effectively preventing auto-doping effect. This method starts with the removal of impurities from the semiconductor substrate having heavily-doped buried layer region and from the inner wall of reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions so as to remove moisture and oxide from the surface of said semiconductor substrate before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate where the dopant atoms have been extracted out. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region.
摘要翻译：本发明涉及一种有效防止自掺杂效应的外延生长方法。该方法首先从具有重掺杂掩埋层区域的半导体衬底和要使用的反应室的内壁去除杂质。然后将半导体衬底装载在清洁的反应室中，以在真空条件下进行预烘烤，以便在从半导体衬底的表面脱附的掺杂剂原子提取之前从所述半导体衬底的表面去除水分和氧化物。接下来，在高温低气体流动条件下，在所述半导体衬底的已经提取出掺杂剂原子的表面上形成第一本征外延层。接下来，在低温和高气体流动条件下，在生长的本征外延层的结构表面上形成所需厚度的第二外延层。最后，冷却后硅片卸载。该方法可以防止在半导体衬底上的外延生长期间的自掺杂效应，从而确保外围电路区域中器件的性能和可靠性。

6. 发明申请

US20130292629A1 PHASE CHANGE MEMORY CELL AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：相变存储单元及其制造方法
公开(公告)号：US20130292629A1
公开(公告)日：2013-11-07
申请号：US13202697
申请日：2011-06-23
申请人： Bo Liu , Zhitang Song , Ting Zhang , Ying Li , Min Zhong , Songlin Feng
发明人： Bo Liu , Zhitang Song , Ting Zhang , Ying Li , Min Zhong , Songlin Feng
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/16 , H01L45/1625 , H01L45/1683
摘要： The present invention provides a phase change memory cell and fabrication method thereof, wherein said phase change memory cell comprises a semiconductor substrate, a first electrode layer, a phase change material layer, a second electrode layer and an extraction electrode, as well as a high resistance material layer used to prevent said phase change material layer from over-corrosion during the chemical mechanical polishing process, and wherein said high resistance material layer has a resistance ten or more times that of the phase change material layer and can be used to prevent phase change material layer from over-corrosion during the chemical mechanical polishing process and thus enhance the memory performance and the yield of phase change memory cell.
摘要翻译：本发明提供一种相变存储单元及其制造方法，其中所述相变存储单元包括半导体衬底，第一电极层，相变材料层，第二电极层和引出电极以及高用于防止所述相变材料层在化学机械抛光工艺期间过度腐蚀的电阻材料层，并且其中所述高电阻材料层具有相变材料层的电阻的十倍或更多倍，并且可用于防止相位在化学机械抛光过程中改变材料层的过度腐蚀，从而提高相变存储单元的记忆性能和产量。

7. 发明申请

US20130334469A1 AL-SB-TE PHASE CHANGE MATERIAL USED FOR PHASE CHANGE MEMORY AND FABRICATION METHOD THEREOF 有权
标题翻译：用于相位变化记忆的AL-SB-TE相变材料及其制造方法
公开(公告)号：US20130334469A1
公开(公告)日：2013-12-19
申请号：US13202953
申请日：2011-06-24
申请人： Cheng Peng , Liangcai Wu , Fang Rao , Zhitang Song , Bo Liu , Xilin Zhou , Min Zhu
发明人： Cheng Peng , Liangcai Wu , Fang Rao , Zhitang Song , Bo Liu , Xilin Zhou , Min Zhu
IPC分类号： G11C11/56 , C23C14/14 , C01B19/00
CPC分类号： G11C11/56 , C01B19/007 , C23C14/0623 , C23C14/14 , C23C14/35 , G11C13/0004 , H01L45/06 , H01L45/144
摘要： The present invention discloses an Al—Sb—Te phase change material used for PCM and fabrication method thereof. Said phase change material, which can be prepared by PVD, CVD, ALD, PLD, EBE, and ED, is a mixture of three elements aluminum (Al), antimony (Sb) and tellurium (Te) with a general formula of Alx(SbyTe1)1-x, where 0
摘要翻译：本发明公开了一种用于PCM的Al-Sb-Te相变材料及其制造方法。可以通过PVD，CVD，ALD，PLD，EBE和ED制备的所述相变材料是三种元素铝（Al），锑（Sb）和碲（Te）的混合物，其通式为Al x（ SbyTe1）1-x，其中0

8. 发明授权

US08920684B2 Al-Sb-Te phase change material used for phase change memory and fabrication method thereof 有权
标题翻译：用于相变存储器的Al-Sb-Te相变材料及其制造方法
公开(公告)号：US08920684B2
公开(公告)日：2014-12-30
申请号：US13202953
申请日：2011-06-24
申请人： Cheng Peng , Liangcai Wu , Feng Rao , Zhitang Song , Bo Liu , Xilin Zhou , Min Zhu
发明人： Cheng Peng , Liangcai Wu , Feng Rao , Zhitang Song , Bo Liu , Xilin Zhou , Min Zhu
IPC分类号： H01B1/02 , G11C11/56 , C23C14/06 , C23C14/35 , C01B19/00 , C23C14/14 , H01L45/00 , G11C13/00
CPC分类号： G11C11/56 , C01B19/007 , C23C14/0623 , C23C14/14 , C23C14/35 , G11C13/0004 , H01L45/06 , H01L45/144
摘要： The present invention discloses an Al—Sb—Te phase change material used for PCM and fabrication method thereof. Said phase change material, which can be prepared by PVD, CVD, ALD, PLD, EBE, and ED, is a mixture of three elements aluminum (Al), antimony (Sb) and tellurium (Te) with a general formula of Alx(SbyTe1)1-x, where 0
摘要翻译：本发明公开了一种用于PCM的Al-Sb-Te相变材料及其制造方法。可以通过PVD，CVD，ALD，PLD，EBE和ED制备的所述相变材料是三种元素铝（Al），锑（Sb）和碲（Te）的混合物，其通式为Al x（ SbyTe1）1-x，其中0

9. 发明申请

US20140008567A1 CHEMICAL MECHANICAL POLISHING SLURRY 审中-公开
标题翻译：化学机械抛光浆
公开(公告)号：US20140008567A1
公开(公告)日：2014-01-09
申请号：US13202669
申请日：2011-06-27
申请人： Liangyong Wang , Zhitang Song , Weili Liu , Bo Liu , Min Zhong , Aodong He
发明人： Liangyong Wang , Zhitang Song , Weili Liu , Bo Liu , Min Zhong , Aodong He
IPC分类号： C09G1/02
CPC分类号： C09G1/02 , C09K3/1463 , H01L45/06 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A chemical mechanical polishing (CMP) slurry used for phase change memory, characterized by comprising polishing particles, oxidizing agents, chelating agents, inhibiting agents, surface active agents, pH adjusting agents/buffering agents and aqueous medium. Compared with the prior art, the present invention provides a chemical mechanical polishing slurry, by which the controllable selectivity of phase change material/bottom dielectric material (1:1 to 180:1) can be achieved and the phase change properties of phase change materials can be maintained after polishing with the polished surface smooth and free from scratch, meeting process requirements of phase change memory.
摘要翻译：用于相变记忆体的化学机械抛光（CMP）浆料，其特征在于包括抛光颗粒，氧化剂，螯合剂，抑制剂，表面活性剂，pH调节剂/缓冲剂和水性介质。与现有技术相比，本发明提供了一种化学机械抛光浆料，通过其可以实现相变材料/底部电介质材料（1：1至180：1）的可控选择性和相变材料的相变性能抛光后可保持抛光表面平滑无刮痕，满足相变记忆的工艺要求。

10. 发明申请

US20150284902A1 POLYURETHANE DISPERSION BASED SYNTHETIC LEATHERS HAVING IMPROVED EMBOSSING CHARACTERISTICS 审中-公开
标题翻译：基于聚氨酯分散体的合成皮革，具有改进的成型特性
公开(公告)号：US20150284902A1
公开(公告)日：2015-10-08
申请号：US14433916
申请日：2012-10-16
申请人： Debkumar BHATTACHARJEE , Weichao GU , Ning KANG , Bo LIU , Yunfei YAN , Hongliang ZHANG , Chao Zhang
发明人： Debkumar Bhattacharjee , Ning Kang , Hong Liang Zhang , Yunfei Yan , Weichao Gu , Bo Liu , Chao Zhang
IPC分类号： D06N3/00 , D06N3/14 , C08J9/00 , C08J9/30 , C08J9/36
CPC分类号： D06N3/0047 , C08G18/10 , C08G18/12 , C08G18/283 , C08G18/4812 , C08G18/4825 , C08G18/4829 , C08G18/6674 , C08G18/706 , C08J9/0028 , C08J9/0033 , C08J9/30 , C08J9/365 , C08J2375/08 , D06N3/0061 , D06N3/0063 , D06N3/0077 , D06N3/14 , D06N3/146 , D06N2211/28 , Y10T428/24438 , C08G18/3228
摘要： Described herein are methods of preparing PUD based, poromeric, synthetic leathers having improved embossing characteristics, the methods comprising: preparing a polyurethane prepolymer, wherein the prepolymer comprises at least one isocyanate resin, and at least two polyols; preparing a first mixture comprising the polyurethane prepolymer, water, a chain extender, and a first surfactant that comprises at least one surfactant; preparing a second mixture comprising the first mixture, a thickening agent, and a second surfactant the comprises at least one surfactant, frothing the second mixture and thereby forming a frothed second mixture; applying the frothed second mixture to a fabric and thereby forming a coated fabric; optionally adjusting the thickness of the frothed third mixture on the fabric; and drying the coated fabric.
摘要翻译：本文描述了制备具有改进的压花特性的基于PUD的多孔体合成革的方法，所述方法包括：制备聚氨酯预聚物，其中所述预聚物包含至少一种异氰酸酯树脂和至少两种多元醇; 制备包含聚氨酯预聚物，水，扩链剂和包含至少一种表面活性剂的第一表面活性剂的第一混合物; 制备包含第一混合物，增稠剂和第二表面活性剂的第二混合物，其包含至少一种表面活性剂，起泡第二混合物，从而形成发泡的第二混合物; 将发泡的第二混合物施加到织物上，从而形成涂布织物; 可选地调节织物上发泡的第三混合物的厚度; 并干燥涂层织物。

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