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1. 发明授权

US09334583B2 Method of preventing auto-doping during epitaxial layer growth by cleaning the reaction chamber with hydrogen chloride 有权
标题翻译：通过用氯化氢清洗反应室来防止外延层生长期间的自掺杂的方法
公开(公告)号：US09334583B2
公开(公告)日：2016-05-10
申请号：US13202944
申请日：2011-06-27
申请人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
发明人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
IPC分类号： C30B25/02 , C30B25/18 , C30B29/06 , C30B23/02 , H01L21/02
CPC分类号： C30B25/186 , C30B23/025 , C30B25/02 , C30B29/06 , H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02661
摘要： An epitaxial growth method for preventing auto-doping effect is presented. This method starts with the removal of impurities from the semiconductor substrate and the reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region.
摘要翻译：提出了一种防止自动掺杂效应的外延生长方法。该方法首先从要使用的半导体衬底和反应室中除去杂质。然后，在从半导体衬底的表面脱离的掺杂剂原子的提取之前，将半导体衬底装载在清洁的反应室中，以在真空条件下预烘烤。接下来，在高温低气流条件下，在所述半导体衬底的表面上形成第一本征外延层。接下来，在低温和高气体流动条件下，在生长的本征外延层的结构表面上形成所需厚度的第二外延层。最后，冷却后硅片卸载。该方法可以防止在半导体衬底上的外延生长期间的自掺杂效应，从而确保外围电路区域中器件的性能和可靠性。

2. 发明申请

US20130189799A1 METHOD OF FABRICATING DUAL TRENCH ISOLATED EPITAXIAL DIODE ARRAY 有权
标题翻译：双层分离分离的外延二极体阵列的方法
公开(公告)号：US20130189799A1
公开(公告)日：2013-07-25
申请号：US13203135
申请日：2011-06-23
申请人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
发明人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
IPC分类号： H01L21/762
CPC分类号： H01L21/76205 , H01L21/76224 , H01L27/0814
摘要： The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory.
摘要翻译：本发明公开了一种制造双沟槽隔离外延二极管阵列的方法。该方法开始于在衬底上形成重掺杂的第一导电类型区域和重掺杂的第二导电类型区域，随后进行外延生长，然后通过深沟槽蚀刻形成二极管阵列字线之间的隔离，并形成通过浅沟槽蚀刻垂直于深沟槽的位线之间的隔离，最后通过离子注入由深和浅沟槽隔离所包围的区域中形成分离的二极管阵列单元。本发明还提供了一种防止由前述的双浅沟槽隔离的外延二极管阵列的相邻字线和位线之间的串扰电流的方法。本发明可用于二极管驱动，高密度，大容量存储器，如相变随机存取存储器，电阻存储器，磁存储器和铁电存储器; 其方法与常规的互补金属氧化物半导体（CMOS）工艺完全兼容，并且由于可以在外围电路形成之前形成二极管阵列，所以不会由于其热处理而引起外围电路的漂移，从而解决了制造高密度，大容量嵌入式相变随机存取存储器的技术挑战。

3. 发明授权

US06429129B1 Method of using silicon rich carbide as a barrier material for fluorinated materials 失效
公开(公告)号：US06429129B1
公开(公告)日：2002-08-06
申请号：US09594415
申请日：2000-06-16
申请人： Licheng Han , Xu Yi , Simon Chooi , Mei Sheng Zhou , Joseph Zhifeng Xie
发明人： Licheng Han , Xu Yi , Simon Chooi , Mei Sheng Zhou , Joseph Zhifeng Xie
IPC分类号： H01L2144
CPC分类号： H01L21/76834 , H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/3127 , H01L21/314 , H01L21/31629 , H01L21/76801 , H01L21/76807 , H01L21/76831 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

4. 发明授权

US06730591B2 Method of using silicon rich carbide as a barrier material for fluorinated materials 失效
标题翻译：使用富碳化碳作为氟化材料的阻挡材料的方法
公开(公告)号：US06730591B2
公开(公告)日：2004-05-04
申请号：US10186532
申请日：2002-07-01
申请人： Licheng Han , Xu Yi , Simon Chooi , Mei Sheng Zhou , Joseph Zhifeng Xie
发明人： Licheng Han , Xu Yi , Simon Chooi , Mei Sheng Zhou , Joseph Zhifeng Xie
IPC分类号： H01L214763
CPC分类号： H01L21/76834 , H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/3127 , H01L21/314 , H01L21/31629 , H01L21/76801 , H01L21/76807 , H01L21/76831 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.
摘要翻译：一种在半导体器件中形成互连结构的方法，包括以下步骤。提供半导体结构。在第一实施例中，在半导体结构上形成至少一条金属线。在金属线和半导体结构之上形成富含碳的碳化物阻挡层。最后，在富含硅的碳化物层上形成可被氟化的介电层。在第二实施例中，在半导体结构上形成至少一个可被氟化的氟化介电层。图案化电介质层以在其中形成开口。在开口内形成富含碳的碳化物阻挡层。在结构上沉积金属化层，填充富含硅的碳化物阻挡层衬里的开口。最后，金属化层可以被平坦化以在富含硅的碳化物阻挡层衬里的开口内形成平坦化的金属结构。

5. 发明授权

US06242344B1 Tri-layer resist method for dual damascene process 失效
标题翻译：双重镶嵌工艺的三层抗蚀剂方法
公开(公告)号：US06242344B1
公开(公告)日：2001-06-05
申请号：US09498986
申请日：2000-02-07
申请人： Leong Tee Koh , Marokkey Raphael Sajan , Tsun-Lung Alex Cheng , Joseph Zhifeng Xie
发明人： Leong Tee Koh , Marokkey Raphael Sajan , Tsun-Lung Alex Cheng , Joseph Zhifeng Xie
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , H01L21/0276 , H01L21/31144 , Y10S438/978
摘要： Under the first embodiment of the invention, a three layer composite layer of insulation is deposited. The trench is etched into this composite layer of insulation followed by a hard bake. The via etch is performed, completing the formation of the dual damascene profile. The created dual damascene profile is transferred into the underlying substrate; the layer of photoresist is removed. Under the second embodiment of the invention, a two layer composite layer of insulation is deposited over a semiconductor surface. The trench is etched into this composite layer of insulation. A layer of positive photoresist is deposited over the second layer of cross-linked negative resist and masked for the via etch. The via etch is performed, the created dual damascene profile is transferred into the underlying substrate. The removal of the layers of patterned photoresist completes the formation of the dual damascene structure.
摘要翻译：在本发明的第一实施例中，沉积三层绝缘层。将沟槽蚀刻到该复合材料层中，然后进行硬烘烤。执行通孔蚀刻，完成双镶嵌轮廓的形成。将所创建的双镶嵌轮廓转移到下面的基底中; 去除光致抗蚀剂层。在本发明的第二实施例中，在半导体表面上沉积两层绝缘复合层。沟槽被蚀刻到这个绝缘复合层中。一层正性光致抗蚀剂沉积在第二层交联的负性抗蚀剂上，并被掩蔽用于通孔蚀刻。执行通孔蚀刻，所创建的双镶嵌轮廓被转移到下面的基底中。图案化光致抗蚀剂层的去除完成了双镶嵌结构的形成。

6. 发明授权

US08476085B1 Method of fabricating dual trench isolated epitaxial diode array 有权
标题翻译：制造双沟槽隔离外延二极管阵列的方法
公开(公告)号：US08476085B1
公开(公告)日：2013-07-02
申请号：US13203135
申请日：2011-06-23
申请人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
发明人： Chao Zhang , Zhitang Song , Xudong Wan , Bo Liu , Guanping Wu , Ting Zhang , Zuoya Yang , Zhifeng Xie
IPC分类号： H01L21/00
CPC分类号： H01L21/76205 , H01L21/76224 , H01L27/0814
摘要： The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory.
摘要翻译：本发明公开了一种制造双沟槽隔离外延二极管阵列的方法。该方法开始于在衬底上形成重掺杂的第一导电类型区域和重掺杂的第二导电类型区域，随后进行外延生长，然后通过深沟槽蚀刻形成二极管阵列字线之间的隔离，并形成通过浅沟槽蚀刻垂直于深沟槽的位线之间的隔离，最后通过离子注入由深和浅沟槽隔离所包围的区域中形成分离的二极管阵列单元。本发明还提供了一种防止由前述的双浅沟槽隔离的外延二极管阵列的相邻字线和位线之间的串扰电流的方法。本发明可用于二极管驱动，高密度，大容量存储器，如相变随机存取存储器，电阻存储器，磁存储器和铁电存储器; 其方法与常规的互补金属氧化物半导体（CMOS）工艺完全兼容，并且由于可以在外围电路形成之前形成二极管阵列，所以不会由于其热处理而引起外围电路的漂移，从而解决了制造高密度，大容量嵌入式相变随机存取存储器的技术挑战。

7. 发明授权

US06424044B1 Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization 有权
标题翻译：使用碳化硼作为铜双镶嵌金属化的蚀刻阻挡层和阻挡层
公开(公告)号：US06424044B1
公开(公告)日：2002-07-23
申请号：US10050697
申请日：2002-01-18
申请人： Licheng M. Han , Xu Yi , Joseph Zhifeng Xie , Mei Sheng Zhou , Simon Chooi
发明人： Licheng M. Han , Xu Yi , Joseph Zhifeng Xie , Mei Sheng Zhou , Simon Chooi
IPC分类号： H01L2348
CPC分类号： H01L21/76834 , H01L21/76807 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.
摘要翻译：公开了一种形成用作铜双镶嵌结构中的屏障和蚀刻停止层的碳化硼层的方法，以及结构本身。除了提供对铜扩散的良好屏障之外，良好的绝缘性能，相对于介电绝缘体的高蚀刻选择性，由于其低介电常数小于5，碳化硼也提供良好的电特性。无定形碳化硼形成于通过在约400℃的沉积温度下引入诸如B 2 H 6，B 5 H 9+的硼源气体和诸如CH 4和C 2 H 6的碳源气体的PECVD室。钝化，蚀刻停止，盖层的任何一种或任何组合镶嵌结构可以包括碳化硼。

8. 发明授权

US06352921B1 Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization 有权
公开(公告)号：US06352921B1
公开(公告)日：2002-03-05
申请号：US09619377
申请日：2000-07-19
申请人： Licheng M. Han , Yi Xu , Joseph Zhifeng Xie , Mei Sheng Zhou , Simon Chooi
发明人： Licheng M. Han , Yi Xu , Joseph Zhifeng Xie , Mei Sheng Zhou , Simon Chooi
IPC分类号： H01L214763
CPC分类号： H01L21/76834 , H01L21/76807 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.

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