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1. 发明授权

US06437411B1 Semiconductor device having chamfered silicide layer and method for manufacturing the same 失效
标题翻译：具有倒角硅化物层的半导体器件及其制造方法
公开(公告)号：US06437411B1
公开(公告)日：2002-08-20
申请号：US09536427
申请日：2000-03-27
申请人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
发明人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
IPC分类号： H01L2976
CPC分类号： H01L21/02071 , H01L21/28114 , H01L21/32134 , H01L21/32137 , H01L21/76897 , H01L23/5258 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns. In the semiconductor device manufacture, in forming undercut regions which define the chamfered upper edges of the metal silicide layer patterns, isotropic dry etching is carried out, wherein the isotropic dry etching can be performed simultaneously with ashing of photoresist patterns, or immediately after the ashing process in the same chamber. In either case, after the ashing of the photoresist patterns, an isotropic wet etching can be carried out immediately after performing an existing stripping process, so as to form the undercut regions.
摘要翻译：具有倒角硅化物层的半导体器件及其制造方法。半导体器件包括：覆盖半导体衬底的第一绝缘层; 包括形成在第一绝缘层上的第一导电层图案的栅结构和形成在第一导电层图案上的第二导电层图案，其中第二导电层图案的下侧基本垂直于半导体衬底的主表面并且第二导电层图案的上侧被倒角; 以及在第二导电层图案上形成有第一宽度W的第二绝缘层，其中第二绝缘层的侧壁悬垂在第二导电层图案的上边缘上。在半导体器件制造中，在形成限定金属硅化物层图案的倒角上边缘的底切区域时，进行各向同性干蚀刻，其中各向同性干蚀刻可以与光致抗蚀剂图案的灰化或灰化之后立即同时进行过程在同一个房间。在任一种情况下，在光致抗蚀剂图案的灰化之后，可以在执行现有的剥离工艺之后立即进行各向同性的湿蚀刻，以形成底切区域。

2. 发明授权

US06740550B2 Methods of manufacturing semiconductor devices having chamfered silicide layers therein 失效
标题翻译：制造其中具有倒角的硅化物层的半导体器件的方法
公开(公告)号：US06740550B2
公开(公告)日：2004-05-25
申请号：US10190086
申请日：2002-07-03
申请人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
发明人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
IPC分类号： H01L218238
CPC分类号： H01L21/02071 , H01L21/28114 , H01L21/32134 , H01L21/32137 , H01L21/76897 , H01L23/5258 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns. In the semiconductor device manufacture, in forming undercut regions which define the chamfered upper edges of the metal silicide layer patterns, isotropic dry etching is carried out, wherein the isotropic dry etching can be performed simultaneously with ashing of photoresist patterns, or immediately after the ashing process in the same chamber. In either case, after the ashing of the photoresist patterns, an isotropic wet etching can be carried out immediately after performing an existing stripping process, so as to form the undercut regions.
摘要翻译：具有倒角硅化物层的半导体器件及其制造方法。半导体器件包括：覆盖半导体衬底的第一绝缘层; 包括形成在第一绝缘层上的第一导电层图案的栅结构和形成在第一导电层图案上的第二导电层图案，其中第二导电层图案的下侧基本垂直于半导体衬底的主表面并且第二导电层图案的上侧被倒角; 以及在第二导电层图案上形成有第一宽度W的第二绝缘层，其中第二绝缘层的侧壁悬垂在第二导电层图案的上边缘上。在半导体器件制造中，在形成限定金属硅化物层图案的倒角上边缘的底切区域时，进行各向同性干蚀刻，其中各向同性干蚀刻可以与光致抗蚀剂图案的灰化或灰化之后立即同时进行过程在同一个房间。在任一种情况下，在光致抗蚀剂图案的灰化之后，可以在执行现有的剥离工艺之后立即执行各向同性的湿蚀刻，以形成底切区域。

3. 发明授权

US08330218B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08330218B2
公开(公告)日：2012-12-11
申请号：US12870913
申请日：2010-08-30
申请人： Jong-ho Park , Hyi-Jeong Park , Hye-mi Kim , Chang-Ki Jeon
发明人： Jong-ho Park , Hyi-Jeong Park , Hye-mi Kim , Chang-Ki Jeon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/8249 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L27/0623 , H01L27/0922 , H01L29/0653 , H01L29/41766 , H01L29/456 , H01L29/66719 , H01L29/66727 , H01L29/7809 , H01L29/7812
摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode.
摘要翻译：提供半导体器件和制造半导体器件的方法。使用DMOS器件的半导体器件包括：形成第一导电型阱的半导体衬底; 形成在所述半导体衬底上的第一导电型栅极电极，所述栅极绝缘层介于所述栅电极和所述半导体衬底之间; 形成在所述半导体基板上并与所述栅电极分离的第二导电型体电极; 形成在所述半导体基板上并与所述栅电极和所述主体电极分离的第一导电型漏电极; 形成在所述体电极下方的所述阱内的第二导电型第一体区域; 第二导电类型的第二主体区域，其从所述第一主体区域延伸到所述栅极绝缘层并形成在所述阱中; 形成在所述第二主体区域中并从所述第一主体区域延伸到所述栅极绝缘层的第一导电型源极区域; 以及第一导电型源电极，其从所述源极区域延伸，以在所述半导体衬底上围绕所述栅极电极，所述绝缘层介于所述源电极和栅电极之间。

4. 发明授权

US06229775B1 Driving method and apparatus for driving light source element independent of a driving mode of an optical pickup 失效
标题翻译：独立于光学拾取器的驱动模式驱动光源元件的驱动方法和装置
公开(公告)号：US06229775B1
公开(公告)日：2001-05-08
申请号：US08225322
申请日：1994-04-08
申请人： Jong-ho Park
发明人： Jong-ho Park
IPC分类号： G11B70045
CPC分类号： G11B7/126 , G11B19/04
摘要： A driving method and apparatus for a light source element of an optical pickup for reading and writing data from and to an optical data includes generating an error signal when a tracking error signal is higher than a first level or is lower than a second level and, if the error signal is active, supplying the light source element with a driving signal suitable for data read operations independent of whether the user selects read mode or write mode. As a result, when there is a tracking error the power of the device signal corresponds to that normally presented during a read mode, and this power is insufficient to write data onto the disc. Thus, data is not written over other desired data when an abnormal tracking error occurs.
摘要翻译：用于从光学数据读取和写入光学数据的光学拾取器的光源元件的驱动方法和装置包括当跟踪误差信号高于第一电平或低于第二电平时产生误差信号，如果误差信号有效，则为光源元件提供适合于数据读取操作的驱动信号，而与用户是否选择读取模式或写入模式无关。结果，当存在跟踪误差时，设备信号的功率对应于在读取模式期间通常呈现的功率，并且该功率不足以将数据写入到盘上。因此，当出现异常跟踪错误时，数据不会写入其他所需数据。

5. 发明授权

US5444005A Method for manufacturing a capacitor of a semiconductor memory device 失效
标题翻译：半导体存储器件的电容器的制造方法
公开(公告)号：US5444005A
公开(公告)日：1995-08-22
申请号：US246277
申请日：1994-05-19
申请人： Yun-gi Kim , Fui-song Kim , Jin-seok Choi , Jong-ho Park
发明人： Yun-gi Kim , Fui-song Kim , Jin-seok Choi , Jong-ho Park
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L28/92 , Y10S438/947
摘要： A method for manufacturing a capacitor of a semiconductor memory device. A conductive layer is formed on the semiconductor substrate and a photoresist pattern is formed on the conductive layer. The conductive layer is etched, using the photoresist pattern as a mask to form a first step-portion in the conductive layer. A first spacer is formed on a sidewall of the photoresist pattern, which may be formed by flowing the photoresist pattern. The conductive layer is etched, using the first spacer as a mask, to form a second step-portion in the conductive layer. The photoresist pattern and the first spacer is removed. A first material layer is formed on the entire surface of the resultant structure and etched to form a second spacer on the sidewalls of the first and second step-portions. The conductive layer is etched, using the second spacer as a mask, to form a storage electrode of a capacitor. Cell capacitance may be increased by a simple process, and the heat cycle may be reduced.
摘要翻译：一种半导体存储器件的电容器的制造方法。在半导体衬底上形成导电层，并且在导电层上形成光刻胶图案。使用光致抗蚀剂图案作为掩模蚀刻导电层，以在导电层中形成第一台阶部分。在光致抗蚀剂图案的侧壁上形成第一间隔物，其可以通过使光致抗蚀剂图案流动而形成。使用第一间隔件作为掩模蚀刻导电层，以在导电层中形成第二台阶部分。去除光致抗蚀剂图案和第一间隔物。第一材料层形成在所得结构的整个表面上并被蚀刻以在第一和第二台阶部分的侧壁上形成第二间隔物。使用第二间隔物作为掩模蚀刻导电层，以形成电容器的存储电极。可以通过简单的工艺来增加电池电容，并且可以减少热循环。

6. 发明申请

US20110240832A1 CYCLIC A/D CONVERTER, IMAGE SENSOR DEVICE, AND METHOD FOR GENERATING DIGITAL SIGNAL FROM ANALOG SIGNAL 有权
标题翻译：循环A / D转换器，图像传感器装置和用于从模拟信号产生数字信号的方法
公开(公告)号：US20110240832A1
公开(公告)日：2011-10-06
申请号：US13124319
申请日：2009-10-15
申请人： Shoji Kawahito , Jong-ho Park , Satoshi Aoyama , Keigo Isobe
发明人： Shoji Kawahito , Jong-ho Park , Satoshi Aoyama , Keigo Isobe
IPC分类号： H01L27/146 , H03M1/12
CPC分类号： H03M1/0695 , H03M1/123 , H03M1/403 , H04N5/3658 , H04N5/3745 , H04N5/378
摘要： A cyclic A/D converter which can reduce the number of reference voltages for D/A conversion is provided. The cyclic A/D converter (11) comprises a gain stage (15), an A/D converter circuit (17), a logic circuit (19), and a D/A converter circuit (21). In an operational action of the gain stage (15), an operational value (VOP) is generated by the use of an operational amplifier circuit (23) and capacitors (25, 27, 29). The gain stage (15) operates as receiving three kinds of voltage signal from the D/A converter circuit (21) by the switching of two kinds of voltage signal (VDA1, VDA2) to be applied to the capacitors (25, 27) in a switching circuit (31). That is, the D/A converter circuit (21) provides a voltage signal (VRH) to the capacitors (25, 27), in response to a value (D=2) of a digital signal (B0, B1), provides voltage signals (VRH, VRL) to the capacitors (25, 27), respectively, in response to a value (D=1) of the signal (B0, B1), and provides the voltage signal (VRL) to the capacitors (25, 27), in response to a value (D=0) of the signal (B0, B1).
摘要翻译：提供了可以减少用于D / A转换的参考电压数量的循环A / D转换器。循环A / D转换器（11）包括增益级（15），A / D转换器电路（17），逻辑电路（19）和D / A转换器电路（21）。在增益级（15）的操作动作中，通过使用运算放大器电路（23）和电容器（25,27,29）产生运算值（VOP）。增益级（15）通过切换要施加到电容器（25,27）的两种电压信号（VDA1，VDA2）来接收来自D / A转换器电路（21）的三种电压信号，开关电路（31）。也就是说，D / A转换器电路（21）响应于数字信号（B0，B1）的值（D = 2）向电容器（25,27）提供电压信号（VRH），提供电压分别响应信号（B0，B1）的值（D = 1）向电容器（25,27）输出信号（VRH，VRL），并将电压信号（VRL）提供给电容器（25,27）响应于信号（B0，B1）的值（D = 0）27）。

7. 发明授权

US07803676B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07803676B2
公开(公告)日：2010-09-28
申请号：US12414172
申请日：2009-03-30
申请人： Jong-ho Park , Chang-Ki Jeon , Hyi-Jeong Park , Hye-mi Kim
发明人： Jong-ho Park , Chang-Ki Jeon , Hyi-Jeong Park , Hye-mi Kim
IPC分类号： H01L21/8238 , H01L21/331 , H01L21/8222
CPC分类号： H01L21/8249 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L27/0623 , H01L27/0922 , H01L29/0653 , H01L29/41766 , H01L29/456 , H01L29/66719 , H01L29/66727 , H01L29/7809 , H01L29/7812
摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode.
摘要翻译：提供半导体器件和制造半导体器件的方法。使用DMOS器件的半导体器件包括：形成第一导电型阱的半导体衬底; 形成在所述半导体衬底上的第一导电型栅极电极，所述栅极绝缘层介于所述栅电极和所述半导体衬底之间; 形成在所述半导体基板上并与所述栅电极分离的第二导电型体电极; 形成在所述半导体基板上并与所述栅电极和所述主体电极分离的第一导电型漏电极; 形成在所述体电极下方的所述阱内的第二导电型第一体区域; 第二导电类型的第二主体区域，其从所述第一主体区域延伸到所述栅极绝缘层并形成在所述阱中; 形成在所述第二主体区域中并从所述第一主体区域延伸到所述栅极绝缘层的第一导电型源极区域; 以及第一导电型源电极，其从所述源极区域延伸，以在所述半导体衬底上围绕所述栅极电极，所述绝缘层介于所述源电极和栅电极之间。

8. 发明授权

US5355020A Semiconductor device having a multi-layer metal contact 失效
标题翻译：具有多层金属接触的半导体器件
公开(公告)号：US5355020A
公开(公告)日：1994-10-11
申请号：US910894
申请日：1992-07-08
申请人： Sang-in Lee , Jeong-in Hong , Jong-ho Park
发明人： Sang-in Lee , Jeong-in Hong , Jong-ho Park
IPC分类号： H01L23/52 , H01L21/027 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/0276 , H01L21/28512 , H01L21/76855 , H01L21/76858 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L23/485 , H01L23/53223 , H01L23/53271 , H01L2924/0002
摘要： A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via) and a first conductive layer formed on the insulating layer which completely fills the opening. The first conductive layer does not produce any Si precipitates in a subsequent heat-treating step for filling the opening with the first conductive layer material. The semiconductor device may further include a second conductive layer having a planarized surface on the first conductive layer. This improves subsequent photolithography. An anti-reflective layer may be formed on the second conductive layer for preventing an unwanted reflection during a photo lithography process. The semiconductor device preferably includes a diffusion barrier layer under the first conductive layer and on the semiconductor substrate, on the insulating layer, and on the inner surface of the opening which prevents a reaction between the first conductive layer and the semiconductor substrate or the insulating layer. A method for forming the wiring layer is also disclosed. Providing a semiconductor device with the wiring layer reduces the leakage current by preventing an Al spiking. Since the first conductive layer undergoes a heat-treatment step at a temperature below the melting point, while flowing into the opening and completely filling it with the first conductive layer material, no void is formed in the opening. Good semiconductor device reliability is ensured in spite of the contact hole being less than 1 .mu.m in size and having an aspect ratio greater than 1.0.
摘要翻译：公开了具有新型接触结构的半导体器件的布线层。半导体器件包括半导体衬底，具有开口（接触孔或通孔）的绝缘层和形成在绝缘层上的完全填充开口的第一导电层。在随后的用第一导电层材料填充开口的热处理步骤中，第一导电层不产生任何Si沉淀物。半导体器件还可以包括在第一导电层上具有平坦化表面的第二导电层。这改善了随后的光刻。可以在第二导电层上形成抗反射层，以防止在光刻工艺期间不期望的反射。半导体器件优选地包括在第一导电层下方，半导体衬底上的绝缘层上的扩散阻挡层，以及防止第一导电层与半导体衬底或绝缘层之间的反应的开口内表面。还公开了一种用于形成布线层的方法。提供具有布线层的半导体器件通过防止Al尖峰来减少泄漏电流。由于第一导电层在低于熔点的温度下经历热处理步骤，同时流入开口并用第一导电层材料完全填充，因此在开口中不形成空隙。尽管接触孔的尺寸小于1μm，纵横比大于1.0，仍然保证良好的半导体器件的可靠性。

9. 发明授权

US08581171B2 Cyclic A/D converter, image sensor device, and method for generating digital signal from analog signal 有权
标题翻译：循环A / D转换器，图像传感器装置以及从模拟信号产生数字信号的方法
公开(公告)号：US08581171B2
公开(公告)日：2013-11-12
申请号：US13124319
申请日：2009-10-15
申请人： Shoji Kawahito , Jong-ho Park , Satoshi Aoyama , Keigo Isobe
发明人： Shoji Kawahito , Jong-ho Park , Satoshi Aoyama , Keigo Isobe
IPC分类号： H01L27/146
CPC分类号： H03M1/0695 , H03M1/123 , H03M1/403 , H04N5/3658 , H04N5/3745 , H04N5/378
摘要： A cyclic A/D converter which can reduce the number of reference voltages for D/A conversion is provided. The cyclic A/D converter (11) comprises a gain stage (15), an A/D converter circuit (17), a logic circuit (19), and a D/A converter circuit (21). In an operational action of the gain stage (15), an operational value (VOP) is generated by the use of an operational amplifier circuit (23) and capacitors (25, 27, 29). The gain stage (15) operates as receiving three kinds of voltage signal from the D/A converter circuit (21) by the switching of two kinds of voltage signal (VDA1, VDA2) to be applied to the capacitors (25, 27) in a switching circuit (31). That is, the D/A converter circuit (21) provides a voltage signal (VRH) to the capacitors (25, 27), in response to a value (D=2) of a digital signal (B0, B1), provides voltage signals (VRH, VRL) to the capacitors (25, 27), respectively, in response to a value (D=1) of the signal (B0, B1), and provides the voltage signal (VRL) to the capacitors (25, 27), in response to a value (D=0) of the signal (B0, B1).
摘要翻译：提供了可以减少用于D / A转换的参考电压数量的循环A / D转换器。循环A / D转换器（11）包括增益级（15），A / D转换器电路（17），逻辑电路（19）和D / A转换器电路（21）。在增益级（15）的操作动作中，通过使用运算放大器电路（23）和电容器（25,27,29）产生运算值（VOP）。增益级（15）通过切换要施加到电容器（25,27）的两种电压信号（VDA1，VDA2）来接收来自D / A转换器电路（21）的三种电压信号，开关电路（31）。也就是说，D / A转换器电路（21）响应于数字信号（B0，B1）的值（D = 2）向电容器（25,27）提供电压信号（VRH），提供电压分别响应信号（B0，B1）的值（D = 1）向电容器（25,27）输出信号（VRH，VRL），并将电压信号（VRL）提供给电容器（25,27）响应于信号（B0，B1）的值（D = 0）27）。

10. 发明授权

US08242007B2 Semiconductor device formed using single polysilicon process and method of fabricating the same 有权
标题翻译：使用单个多晶硅工艺形成的半导体器件及其制造方法
公开(公告)号：US08242007B2
公开(公告)日：2012-08-14
申请号：US12401693
申请日：2009-03-11
申请人： Jong-ho Park , Chang-ki Jeon , Hyi-jeong Park
发明人： Jong-ho Park , Chang-ki Jeon , Hyi-jeong Park
IPC分类号： H01L27/06 , H01L21/60
CPC分类号： H01L21/8249 , H01L21/2256 , H01L21/823814 , H01L27/0623
摘要： Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions.
摘要翻译：提供了包括使用掺杂多晶硅工艺形成的源极/漏极和栅极的半导体器件，以及制造半导体器件的方法。该方法包括：在第一导电型外延层的有源区的一部分上形成栅极绝缘层; 在外延层上形成导电层; 将第二导电类型的高浓度杂质注入到第一绝缘层的栅绝缘层上的导电层的第一部分和导电层的第二部分上; 图案化导电层; 在所述外延层上形成第二绝缘层，在所述第二导电图案之下形成所述第二导电类型的高浓度杂质区; 以及将第二导电类型的低浓度杂质注入到栅极结构和高浓度杂质区之间的外延层中。

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