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1. 发明授权

US06740550B2 Methods of manufacturing semiconductor devices having chamfered silicide layers therein 失效
标题翻译：制造其中具有倒角的硅化物层的半导体器件的方法
公开(公告)号：US06740550B2
公开(公告)日：2004-05-25
申请号：US10190086
申请日：2002-07-03
申请人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
发明人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
IPC分类号： H01L218238
CPC分类号： H01L21/02071 , H01L21/28114 , H01L21/32134 , H01L21/32137 , H01L21/76897 , H01L23/5258 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns. In the semiconductor device manufacture, in forming undercut regions which define the chamfered upper edges of the metal silicide layer patterns, isotropic dry etching is carried out, wherein the isotropic dry etching can be performed simultaneously with ashing of photoresist patterns, or immediately after the ashing process in the same chamber. In either case, after the ashing of the photoresist patterns, an isotropic wet etching can be carried out immediately after performing an existing stripping process, so as to form the undercut regions.
摘要翻译：具有倒角硅化物层的半导体器件及其制造方法。半导体器件包括：覆盖半导体衬底的第一绝缘层; 包括形成在第一绝缘层上的第一导电层图案的栅结构和形成在第一导电层图案上的第二导电层图案，其中第二导电层图案的下侧基本垂直于半导体衬底的主表面并且第二导电层图案的上侧被倒角; 以及在第二导电层图案上形成有第一宽度W的第二绝缘层，其中第二绝缘层的侧壁悬垂在第二导电层图案的上边缘上。在半导体器件制造中，在形成限定金属硅化物层图案的倒角上边缘的底切区域时，进行各向同性干蚀刻，其中各向同性干蚀刻可以与光致抗蚀剂图案的灰化或灰化之后立即同时进行过程在同一个房间。在任一种情况下，在光致抗蚀剂图案的灰化之后，可以在执行现有的剥离工艺之后立即执行各向同性的湿蚀刻，以形成底切区域。

2. 发明授权

US06437411B1 Semiconductor device having chamfered silicide layer and method for manufacturing the same 失效
标题翻译：具有倒角硅化物层的半导体器件及其制造方法
公开(公告)号：US06437411B1
公开(公告)日：2002-08-20
申请号：US09536427
申请日：2000-03-27
申请人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
发明人： Chang-won Choi , Dae-hyuk Chung , Woo-sik Kim , Shin-woo Nam , Yeo-cheol Yoon , Bum-su Kim , Jong-ho Park , Ji-hwan Choi
IPC分类号： H01L2976
CPC分类号： H01L21/02071 , H01L21/28114 , H01L21/32134 , H01L21/32137 , H01L21/76897 , H01L23/5258 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns. In the semiconductor device manufacture, in forming undercut regions which define the chamfered upper edges of the metal silicide layer patterns, isotropic dry etching is carried out, wherein the isotropic dry etching can be performed simultaneously with ashing of photoresist patterns, or immediately after the ashing process in the same chamber. In either case, after the ashing of the photoresist patterns, an isotropic wet etching can be carried out immediately after performing an existing stripping process, so as to form the undercut regions.
摘要翻译：具有倒角硅化物层的半导体器件及其制造方法。半导体器件包括：覆盖半导体衬底的第一绝缘层; 包括形成在第一绝缘层上的第一导电层图案的栅结构和形成在第一导电层图案上的第二导电层图案，其中第二导电层图案的下侧基本垂直于半导体衬底的主表面并且第二导电层图案的上侧被倒角; 以及在第二导电层图案上形成有第一宽度W的第二绝缘层，其中第二绝缘层的侧壁悬垂在第二导电层图案的上边缘上。在半导体器件制造中，在形成限定金属硅化物层图案的倒角上边缘的底切区域时，进行各向同性干蚀刻，其中各向同性干蚀刻可以与光致抗蚀剂图案的灰化或灰化之后立即同时进行过程在同一个房间。在任一种情况下，在光致抗蚀剂图案的灰化之后，可以在执行现有的剥离工艺之后立即进行各向同性的湿蚀刻，以形成底切区域。

3. 发明授权

US06406967B1 Method for manufacturing cylindrical storage electrode of semiconductor device 失效
标题翻译：半导体器件的圆柱形存储电极的制造方法
公开(公告)号：US06406967B1
公开(公告)日：2002-06-18
申请号：US09632583
申请日：2000-08-07
申请人： Dae-hyuk Chung , Chang-lyong Song
发明人： Dae-hyuk Chung , Chang-lyong Song
IPC分类号： H01L2120
CPC分类号： H01L27/10855 , H01L28/91
摘要： A method for manufacturing a cylindrical storage electrode of a semiconductor device includes forming a contact pad to be connected to an active region of a semiconductor substrate in an interlayer insulator film on the semiconductor substrate. Then, a silicon nitride layer as an etching stop layer is formed on the contact pad. Next, an insulating layer is formed on the silicon nitride layer. A portion of the surface of the silicon nitride layer is exposed by partially removing the insulating layer. Then, the exposed portion of the silicon nitride layer is removed using a wet etching process using a predetermined etchant to expose the surface of the contact pad. A conductive layer for a storage electrode is formed on the insulating layer and the surface of the exposed contact pad. Finally, a cylindrical storage electrode is completed by removing the upper portion of the conductive layer for a storage electrode, the insulating layer and the silicon nitride layer.
摘要翻译：一种用于制造半导体器件的圆柱形存储电极的方法包括在半导体衬底上的层间绝缘膜中形成要连接到半导体衬底的有源区的接触焊盘。然后，在接触焊盘上形成作为蚀刻停止层的氮化硅层。接下来，在氮化硅层上形成绝缘层。通过部分去除绝缘层来暴露氮化硅层表面的一部分。然后，使用预定的蚀刻剂使用湿式蚀刻工艺去除氮化硅层的暴露部分，以暴露接触焊盘的表面。在绝缘层和暴露的接触垫的表面上形成用于存储电极的导电层。最后，通过去除用于存储电极，绝缘层和氮化硅层的导电层的上部来完成圆柱形存储电极。

4. 发明授权

US06369008B1 Cleaning solutions for removing contaminants from the surfaces of semiconductor substrates and cleaning methods using the same 失效
标题翻译：用于从半导体衬底的表面去除污染物的清洁溶液和使用其的清洁方法
公开(公告)号：US06369008B1
公开(公告)日：2002-04-09
申请号：US09665622
申请日：2000-09-19
申请人： Heon-jae Ha , Dae-hyuk Chung , In-seak Hwang , Yong-sun Ko
发明人： Heon-jae Ha , Dae-hyuk Chung , In-seak Hwang , Yong-sun Ko
IPC分类号： C11D710
CPC分类号： C11D3/3947 , C11D7/08 , C11D7/10 , C11D11/0047 , H01L21/02063 , H01L21/76814 , H01L21/76897
摘要： Cleaning solutions for removing contaminants from semiconductor substrates are provided and include from about 0.08 to about 0.1 percent by weight of hydrogen fluoride; from about 0.5 to about 0.6 percent by weight of ammonium fluoride; from about 24.9 to about 49.7 percent by weight of hydrogen peroxide; and from about 49.6 to about 74.5 percent by weight of water.
摘要翻译：提供了用于从半导体衬底去除污染物的清洁溶液，包括约0.08至约0.1重量％的氟化氢; 约0.5至约0.6重量％的氟化铵; 约24.9至约49.7重量％的过氧化氢; 和约49.6至约74.5重量％的水。

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