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1. 发明授权

US06819129B2 Method and apparatus for testing a non-standard memory device under actual operating conditions 有权
标题翻译：在实际操作条件下测试非标准存储器件的方法和装置
公开(公告)号：US06819129B2
公开(公告)日：2004-11-16
申请号：US10314474
申请日：2002-12-05
申请人： Chang-Nyun Kim , Sang-Jun Park , Sun-Ju Kim , Hyun-Ho Park , Jin-Seop Seo
发明人： Chang-Nyun Kim , Sang-Jun Park , Sun-Ju Kim , Hyun-Ho Park , Jin-Seop Seo
IPC分类号： G01R3102
CPC分类号： G11C29/56016 , G11C29/48
摘要： A method and apparatus for testing memory devices under actual operating conditions can accommodate non-standard memory devices through the use of an interface board that adapts a non-standard pin configuration to a standard pin configuration on a test substrate. The interface board can include a first surface on which to mount the non-standard device, a pin matching circuit, and a second surface constructed and arranged to couple the pin matching circuit to a standard pin configuration. The interface board can be mounted directly on the test substrate, or coupled to the test substrate through various arrangements of sockets, connection boards, and supports.
摘要翻译：用于在实际操作条件下测试存储器件的方法和装置可以通过使用将非标准引脚配置适配到测试基板上的标准引脚配置的接口板来适应非标准存储器件。接口板可以包括第一表面，其上安装非标准器件，引脚匹配电路以及构造和布置成将引脚匹配电路耦合到标准引脚配置的第二表面。接口板可以直接安装在测试基板上，或者通过插座，连接板和支架的各种布置耦合到测试基板。

2. 发明授权

US07256594B2 Method and apparatus for testing semiconductor devices using the back side of a circuit board 有权
标题翻译：使用电路板背面测试半导体器件的方法和装置
公开(公告)号：US07256594B2
公开(公告)日：2007-08-14
申请号：US10876346
申请日：2004-06-23
申请人： Chang-Nyun Kim , Sun-Ju Kim , Jong-Hyun Kim , Chung-Koo Yoon , Sang-Jun Park
发明人： Chang-Nyun Kim , Sun-Ju Kim , Jong-Hyun Kim , Chung-Koo Yoon , Sang-Jun Park
IPC分类号： G01R31/02
CPC分类号： G01R31/2886 , G01R1/0408 , G11C29/48 , G11C29/56
摘要： A test system for a semiconductor device couples the device to the back side of a circuit board, thereby allowing the device to be tested under actual operating conditions while providing adequate clearance around the device to accommodate automatic handling equipment, and also reducing signal delay and distortion. A system in accordance with the present invention includes a circuit board having circuitry adapted to provide an actual operating environment for the semiconductor device, as for example, a low cost mother board for testing memory devices. The device is coupled to the back side of the circuit board through test terminals formed on the back side of the board. An interface board can be used to correct the pin arrangements, which are reversed because they protrude from the back side of the board, and to compensate for the environmental differences caused by use of sockets and additional equipment on the interface board.
摘要翻译：用于半导体器件的测试系统将设备耦合到电路板的背面，从而允许在实际操作条件下测试设备，同时在设备周围提供足够的间隙以适应自动处理设备，并且还减少信号延迟和失真。根据本发明的系统包括具有适于为半导体器件提供实际操作环境的电路的电路板，例如用于测试存储器件的低成本母板。该器件通过形成在电路板背面的测试端子耦合到电路板的背面。可以使用接口板来校正引脚布置，这是因为它们从板的背面突出而相反，并且补偿了在接口板上使用插座和附加设备引起的环境差异。

3. 发明授权

US06771088B2 Method and apparatus for testing semiconductor devices using the back side of a circuit board 有权
公开(公告)号：US06771088B2
公开(公告)日：2004-08-03
申请号：US09752998
申请日：2000-12-28
申请人： Chang-Nyun Kim , Sun-Ju Kim , Jong-Hyun Kim , Chung-Koo Yoon , Sang-Jun Park
发明人： Chang-Nyun Kim , Sun-Ju Kim , Jong-Hyun Kim , Chung-Koo Yoon , Sang-Jun Park
IPC分类号： G01R3128
CPC分类号： G01R31/2886 , G01R1/0408 , G11C29/48 , G11C29/56
摘要： A test system for a semiconductor device couples the device to the back side of a circuit board, thereby allowing the device to be tested under actual operating conditions while providing adequate clearance around the device to accommodate automatic handling equipment, and also reducing signal delay and distortion. A system in accordance with the present invention includes a circuit board having circuitry adapted to provide an actual operating environment for the semiconductor device, as for example, a low cost mother board for testing memory devices. The device is coupled to the back side of the circuit board through test terminals formed on the back side of the board. An interface board can be used to correct the pin arrangements, which are reversed because they protrude from the back side of the board, and to compensate for the environmental differences caused by use of sockets and additional equipment on the interface board.

4. 发明申请

US20050057272A1 Method and apparatus for testing semiconductor devices using an actual board-type product 有权
标题翻译：使用实际板式产品测试半导体器件的方法和装置
公开(公告)号：US20050057272A1
公开(公告)日：2005-03-17
申请号：US10982646
申请日：2004-11-03
申请人： Sang-Jun Park , Chang-Nyun Kim , Hyun-Ho Park , Nam-Sik Jeong , Jong-Hyun Kim , Chung-Koo Yoon
发明人： Sang-Jun Park , Chang-Nyun Kim , Hyun-Ho Park , Nam-Sik Jeong , Jong-Hyun Kim , Chung-Koo Yoon
IPC分类号： G01R31/28 , G01R31/319 , G11C29/48 , G11C29/56 , G01R31/26
CPC分类号： G11C29/48 , G01R31/31905 , G11C29/56016
摘要： A method and apparatus for testing semiconductor devices allows devices to be tested under actual operating conditions by interfacing the devices to an actual board-type product. The semiconductor devices are interfaced to the board-type product with a test board that includes a mounting unit such as a socket or pattern of conductive lands that allows the devices being tested can be easily mounted to and removed from the test board with minimal effort and signal degradation. An interface circuit on the test board compensates for environmental differences between the board-type product and the mounting unit. For example, the interface circuit can include a clock distribution circuit, which utilizes a phase locked loop, and a register circuit to compensate for electrical loading caused by the device mounting unit, and to provide the proper timing margins between clock signals and control signals applied to the semiconductor devices. A power control circuit can be used to manipulate the supply voltage applied to the semiconductor devices, thereby providing a voltage margin screening function.
摘要翻译：用于测试半导体器件的方法和装置允许通过将器件与实际的板式产品相连接，在实际操作条件下测试器件。半导体器件与板式产品接口，该测试板包括诸如插座或导电焊盘图案的安装单元，其允许被测试的器件能够以最小的努力容易地安装到测试板并从测试板移除，信号劣化。测试板上的接口电路补偿了板式产品和安装单元之间的环境差异。例如，接口电路可以包括使用锁相环的时钟分配电路和用于补偿由器件安装单元引起的电负载的寄存器电路，并且提供时钟信号和施加的控制信号之间的适当时序余量到半导体器件。可以使用功率控制电路来操纵施加到半导体器件的电源电压，从而提供电压裕度屏蔽功能。

5. 发明授权

US07075325B2 Method and apparatus for testing semiconductor devices using an actual board-type product 有权
标题翻译：使用实际板式产品测试半导体器件的方法和装置
公开(公告)号：US07075325B2
公开(公告)日：2006-07-11
申请号：US10982646
申请日：2004-11-03
申请人： Sang-Jun Park , Chang-Nyun Kim , Hyun-Ho Park , Nam-Sik Jeong , Jong-Hyun Kim , Chung-Koo Yoon
发明人： Sang-Jun Park , Chang-Nyun Kim , Hyun-Ho Park , Nam-Sik Jeong , Jong-Hyun Kim , Chung-Koo Yoon
IPC分类号： G01R31/26
CPC分类号： G11C29/48 , G01R31/31905 , G11C29/56016
摘要： Semiconductor devices are tested under actual operating conditions by interfacing the devices to an actual board-type product, for example, through a test board tat includes a mounting unit such as a socket or pattern of conductive lands that allows the devices being tested to be mounted to and removed from the test board with minimal effort and signal degradation. An interface circuit on the test board compensates for environmental differences between the board-type product and the mounting unit. For example, the interface circuit can include a clock distribution circuit, which utilizes a phase locked loop, and a register circuit to compensate for electrical loading caused by the device mounting unit, and to provide the proper timing margins between clock signals and control signals applied to the semiconductor devices. A power control circuit can be used to manipulate the supply voltage thereby providing a voltage margin screening function.
摘要翻译：半导体器件在实际操作条件下通过将器件连接到实际的板式产品来测试，例如，通过包括诸如插座的安装单元或允许被测试器件被安装的导电焊盘图案的测试板以最小的努力和信号衰减从测试板移除和移除。测试板上的接口电路补偿了板式产品和安装单元之间的环境差异。例如，接口电路可以包括使用锁相环的时钟分配电路和用于补偿由器件安装单元引起的电负载的寄存器电路，并且提供时钟信号和施加的控制信号之间的适当时序余量到半导体器件。功率控制电路可用于操纵电源电压，从而提供电压裕度屏蔽功能。

6. 发明授权

US06833721B2 Method and apparatus for testing semiconductor devices using an actual board-type product 有权
标题翻译：使用实际板式产品测试半导体器件的方法和装置
公开(公告)号：US06833721B2
公开(公告)日：2004-12-21
申请号：US09733336
申请日：2000-12-08
申请人： Sang-Jun Park , Chang-Nyun Kim , Hyun-Ho Park , Nam-Sik Jeong , Jong-Hyun Kim , Chung-Koo Yoon
发明人： Sang-Jun Park , Chang-Nyun Kim , Hyun-Ho Park , Nam-Sik Jeong , Jong-Hyun Kim , Chung-Koo Yoon
IPC分类号： G01R3126
CPC分类号： G11C29/48 , G01R31/31905 , G11C29/56016
摘要： Embodiments of the invention allow semiconductor devices to be tested under actual operating conditions by interfacing the devices to an actual board-type product. The devices are interfaced to the board-type product with a test board that includes a mounting unit such as a socket or pattern of conductive lands that allows the devices to be easily mounted to and removed from the test board with minimal effort and signal degradation. An interface circuit on the test board compensates for environmental differences between the board-type product and the mounting unit. A power control circuit can be used to manipulate the supply voltage applied to the semiconductor devices, thereby providing a voltage margin screening function.
摘要翻译：本发明的实施例允许半导体器件在实际操作条件下通过将器件连接到实际的板式产品来测试。这些设备与板式产品接口，测试板包括一个安装单元，例如插座或导电焊盘图案，允许设备以最小的努力和信号衰减方便地安装到测试板上并从测试板上移除。测试板上的接口电路补偿了板式产品和安装单元之间的环境差异。可以使用功率控制电路来操纵施加到半导体器件的电源电压，从而提供电压裕度屏蔽功能。

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