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1. 发明授权

US5758116A Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions 失效
标题翻译：指令长度解码器，用于产生可变长度指令之间的标识边界的输出长度标记
公开(公告)号：US5758116A
公开(公告)日：1998-05-26
申请号：US316208
申请日：1994-09-30
申请人： Chan W. Lee , Gary L. Brown , Adrian L. Carbine , Ashwani Kumar Gupta
发明人： Chan W. Lee , Gary L. Brown , Adrian L. Carbine , Ashwani Kumar Gupta
IPC分类号： G06F9/30 , G06F9/38 , G06F12/04
CPC分类号： G06F9/30152 , G06F9/3816 , G06F9/382
摘要： A circuit and method for supplying output length marks indicative of the first bytes and last bytes of instructions in a block of instruction code to an instruction decoder. A block of instruction code is input to an input buffer. A plurality of programmable logic arrays (PLAs) is coupled to receive predetermined sets of bytes from the input buffer and to provide instruction information at an output. The output of the PLAs is coupled to fast carry chain circuitry, which serially processes the information from the PLAs and provides a START mark upon each finding of a first byte of an instruction and an END mark upon each finding of a last byte of an instruction. Length information is provided to wraparound logic for length calculations spanning into the next input buffer of instruction code. A FCC latch latches the output length marks from the fast carry chain circuitry and provides an output to the instruction decoder. If a length-varying prefix and a matching length-varying opcode are both present in an instruction, processing in the fast carry chain circuitry is aborted, and processing in slow carry chain circuitry is started. The slow carry chain circuitry processes information from a subset of the input buffer at a time, and thus requires more than one iteration, with a different set of PLA inputs provided by a multiplexer upon each iteration. A SCC latch latches the output length marks from the slow carry chain circuitry and provides an output to the instruction decoder.
摘要翻译：一种用于将指示指令代码块中的指令的第一字节和最后字节的输出长度标记提供给指令解码器的电路和方法。指令代码块被输入到输入缓冲器。多个可编程逻辑阵列（PLAs）被耦合以从输入缓冲器接收预定的字节集合并在输出端提供指令信息。 PLA的输出耦合到快速进位链电路，其快速处理来自PLAs的信息，并且在每次发现指令的第一个字节时提供START标记，并且在每次发现指令的最后一个字节时提供END标记。长度信息被提供给跨越到指令代码的下一个输入缓冲器的长度计算的环绕逻辑。 FCC锁存器锁存来自快速进位链电路的输出长度标记，并向指令解码器提供输出。如果长度变化的前缀和匹配的长度变化的操作码都存在于指令中，则快速进位链电路中的处理被中止，并且慢进位链电路中的处理开始。慢进位链电路一次处理来自输入缓冲器的子集的信息，因此需要多于一次的迭代，在每次迭代时由多路复用器提供的不同的PLA输入集合。 SCC锁存器从慢进位链电路锁存输出长度标记，并向指令解码器提供输出。

2. 发明授权

US5630083A Decoder for decoding multiple instructions in parallel 失效
标题翻译：解码器并行解码多条指令
公开(公告)号：US5630083A
公开(公告)日：1997-05-13
申请号：US673897
申请日：1996-07-03
申请人： Adrian L. Carbine , Gary L. Brown , Donald D. Parker
发明人： Adrian L. Carbine , Gary L. Brown , Donald D. Parker
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/28 , G06F9/30145 , G06F9/3822
摘要： A decoder for decoding multiple instructions in parallel, including a full decoder that can decode an instruction into multiple micro-operations, and a partial decoder that can decode a subset of the full instruction set.
摘要翻译：一种用于并行解码多个指令的解码器，包括可以将指令解码为多个微操作的完整解码器，以及可解码整个指令集的子集的部分解码器。

3. 发明授权

US5668985A Decoder having a split queue system for processing intstructions in a first queue separate from their associated data processed in a second queue 失效
标题翻译：解码器具有分离队列系统，用于处理与在第二队列中处理的相关联的数据分离的第一队列中的指令
公开(公告)号：US5668985A
公开(公告)日：1997-09-16
申请号：US204992
申请日：1994-03-01
申请人： Adrian L. Carbine , Gary L. Brown , Bradley D. Hoyt , Donald D. Parker , Rajesh Kumar
发明人： Adrian L. Carbine , Gary L. Brown , Bradley D. Hoyt , Donald D. Parker , Rajesh Kumar
IPC分类号： G06F9/22 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/223 , G06F9/30145 , G06F9/3875
摘要： A split queue system for a decoder that supplies one or more micro-operations and data associated with the micro-operations. A main queue is coupled to receive one or more micro-operations from the decoder, and supply it to a next processing stage to provide a process micro-operation. A shadow queue is coupled to receive data associated with the micro-operation, in the same cycle that the micro-operation is supplied to the main queue. A control circuit is coupled to the main queue for issuing micro-operation from the main queue into the next processing stage in a first cycle, and in a second cycle issuing, the micro-operation therefrom. Also in the second cycle, the control circuit issues the data associated with the micro-operation from the shadow queue, so that the data is synchronized with its associated processed micro-operation.
摘要翻译：用于解码器的分离队列系统，其提供与微操作相关联的一个或多个微操作和数据。主队列被耦合以从解码器接收一个或多个微操作，并将其提供给下一个处理阶段以提供处理微操作。耦合影子队列以在微操作被提供给主队列的同一周期中接收与微操作相关联的数据。控制电路耦合到主队列，用于在第一周期中从主队列发出微操作到下一个处理级，并且在第二周期中从其发出微操作。同样在第二周期中，控制电路从影子队列发出与微操作相关联的数据，使得数据与其相关联的处理的微操作同步。

4. 发明授权

US5673427A Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue 失效
标题翻译：将从并行解码器接收的有效微操作打包到输出队列的相邻位置
公开(公告)号：US5673427A
公开(公告)日：1997-09-30
申请号：US675419
申请日：1996-07-03
申请人： Gary L. Brown , Adrian L. Carbine , Donald D. Parker
发明人： Gary L. Brown , Adrian L. Carbine , Donald D. Parker
IPC分类号： G06F9/28 , G06F9/30 , G06F9/38 , G06F9/22
CPC分类号： G06F9/30167 , G06F9/28 , G06F9/30036 , G06F9/3004 , G06F9/383
摘要： A micro-operation queue for holding a plurality of micro-operations supplied simultaneously by a decoder. A plurality of packing multiplexers are coupled to receive the plurality of micro-operations, and valid bits associated therewith, and to provide packed micro-operation data output in which the valid micro-operations are positioned in adjacent outputs, thereby removing all empty slots. A FIFO queue receives the packed data, in responsive to valid micro-operations, stores the valid micro-operations starting with the next available empty queue location. An embodiment described in which the FIFO queue includes a circular queue with a plurality of entries. In one embodiment, alignment multiplexers for the circular queue are combined with the packing multiplexers, to provide a single-level plurality of packing and aligning multiplexers that has a control system that, responsive to the valid bits of the packed data and the next available pointer of the circular queue, packs, aligns, and stores the micro-operations into the circular queue from where they can be issued.
摘要翻译：一种用于保持由解码器同时提供的多个微操作的微操作队列。耦合多个封装多路复用器以接收多个微操作以及与其相关联的有效位，并且提供压缩的微操作数据输出，其中有效微操作位于相邻的输出端，从而去除所有的空槽。 FIFO队列接收打包数据，响应于有效的微操作，存储从下一个可用空队列位置开始的有效微操作。所描述的实施例，其中FIFO队列包括具有多个条目的循环队列。在一个实施例中，用于循环队列的对准多路复用器与打包多路复用器组合，以提供具有控制系统的单级多个打包和对准多路复用器，该控制系统响应于打包数据的有效位和下一个可用指针的循环队列，将微操作打包，对齐并存储到可以从其发布的循环队列中。

5. 发明授权

US5581717A Decoding circuit and method providing immediate data for a micro-operation issued from a decoder 失效
标题翻译：解码电路和方法提供从解码器发出的微操作的即时数据
公开(公告)号：US5581717A
公开(公告)日：1996-12-03
申请号：US204742
申请日：1994-03-01
申请人： Darrell D. Boggs , Gary L. Brown , Donald D. Parker
发明人： Darrell D. Boggs , Gary L. Brown , Donald D. Parker
IPC分类号： G06F9/22 , G06F9/30 , G06F9/302 , G06F9/35 , G06F9/34 , G06F9/40
CPC分类号： G06F9/3001 , G06F9/223 , G06F9/30145 , G06F9/30167 , G06F9/35
摘要： Decoding circuitry and a method supplying an immediate field that is issued from a decoder. A macroinstruction is supplied to the decoding circuit, which generates a first micro-operation that includes a first aliasing field and a first immediate field. The first aliasing field indicates the source of the micro-operation that will eventually be issued from the decoder. If the source is the first immediate field, then the alias field is further examined to determine the interpretation to be placed upon the data. The data may be interpreted literally, or as an address into a constant ROM, thereby providing an ability to output wide, 32-bit immediate data from a narrower, 9-bit input addresses. Additional sources for immediate data include macro-alias registers, macro-branch information, and micro-branch information.
摘要翻译：解码电路和提供从解码器发出的立即字段的方法。宏指令被提供给解码电路，其产生包括第一混叠字段和第一立即字段的第一微操作。第一个混叠字段指示最终将从解码器发出的微操作的源。如果源是第一个立即字段，则进一步检查别名字段以确定要放置在数据上的解释。数据可以被字面地解释，或者作为一个地址到恒定的ROM中，从而提供从较窄的9位输入地址输出宽的32位立即数据的能力。即时数据的其他来源包括宏别名寄存器，宏分支信息和微分支信息。

6. 发明授权

US5051893A System for processing data to facilitate the creation of executable images 失效
标题翻译：用于处理数据以便于创建可执行映像的系统
公开(公告)号：US5051893A
公开(公告)日：1991-09-24
申请号：US217322
申请日：1988-07-11
申请人： J. David Tenny , Jeff Piazza , Gary L. Brown , Paul C. Anagnostropoulos , Bruce A. Foster , Beryl E. Nelson , Walter van Roggen
发明人： J. David Tenny , Jeff Piazza , Gary L. Brown , Paul C. Anagnostropoulos , Bruce A. Foster , Beryl E. Nelson , Walter van Roggen
IPC分类号： G06F9/45 , G06F9/44 , G06F9/445
CPC分类号： G06F8/54
摘要： A system for processing code contained in one or more selected files, before the code is linked to form an executable image, features means for determining the locations in memory where the code will be stored after it is linked, and means for revising the code to correspond to the determined memory locations. The object code files include code comprising a programming environment, such as LISP, and code input by a user. The user can delete selected portions of the programming environment. Read only, static, and dynamic memory are utilized and each portion of the code input by the user is evaluated to determine which memory is most appropriate.
摘要翻译：一种用于在所述代码被链接以形成可执行图像之前处理包含在一个或多个所选文件中的代码的系统，用于确定所述代码在链接之后将被存储的存储器中的位置的特征装置，以及用于将代码修改为对应于确定的记忆位置。目标代码文件包括包括编程环境（例如LISP）和用户输入的代码的代码。用户可以删除编程环境的所选部分。使用只读，静态和动态存储器，并评估用户输入的代码的每个部分，以确定哪个内存最合适。

7. 发明授权

US5867701A System for inserting a supplemental micro-operation flow into a macroinstruction-generated micro-operation flow 失效
标题翻译：用于将补充微操作流插入到宏指令生成的微操作流中的系统
公开(公告)号：US5867701A
公开(公告)日：1999-02-02
申请号：US937097
申请日：1997-09-24
申请人： Gary L. Brown , R. Guru Prasadh
发明人： Gary L. Brown , R. Guru Prasadh
IPC分类号： G06F9/26 , G06F9/30 , G06F9/318 , G06F9/38 , G06F3/00
CPC分类号： G06F9/30185 , G06F9/268 , G06F9/30145 , G06F9/3861
摘要： A system for inserting a supplemental micro-operation sequence into a macroinstruction-generated micro-operation flow provides a versatile, flexible mechanism for early pipeline stages of a microprocessor to pass control signals, data, and other information to later pipeline stages. The mechanism is useful to maintain precise timing of a fault model in pipelined processors. A method includes the step of detecting the occurrence of a predetermined uop-inserting event and, responsive thereto, generating a control signal to a uop insertion unit. Responsive thereto, the uop insertion unit supplies signals to a decoder which, responsive thereto, decodes the signal encoded within the signal to provide the inserted uop sequence, which is inserted in a position within the macroinstruction-generated micro-operation flow predetermined by the uop-inserting event.
摘要翻译：用于将补充微操作序列插入到宏指令生成的微操作流中的系统为微处理器的早期流水线阶段提供通用的，灵活的机制，以将控制信号，数据和其他信息传递到后期流水线级。该机制有助于维持流水线处理器中故障模型的精确定时。一种方法包括检测预定的uop插入事件的发生的步骤，并且响应于此，向uop插入单元生成控制信号。响应于此，引导单元向解码器提供信号，解码器响应于此解码在信号内编码的信号，以提供插入的uop序列，其插入在由uop预定的宏指令生成的微操作流程内的位置 - 插入事件。

8. 发明授权

US5445582A Hand exerciser device 失效
标题翻译：手动锻炼装置
公开(公告)号：US5445582A
公开(公告)日：1995-08-29
申请号：US177254
申请日：1994-01-01
申请人： Gary L. Brown
发明人： Gary L. Brown
IPC分类号： A63B21/002 , A63B23/00 , A63B23/16 , A63B21/02
CPC分类号： A63B23/16 , A63B21/4025 , A63B21/00047 , A63B21/0023
摘要： An exerciser device having a band, a wrist securing member connected to the band such that the band extends outwardly of the wrist securing member, and finger engagement member affixed to the band at a position generally opposed to the wrist securing member. The wrist securing member serves for removable attachment around a human wrist. The finger engagement member extends inwardly of the band. A thumb engagement member is affixed to the band at a position generally between the finger engagement member and the wrist securing member. The band has a generally rigid and generally circular configuration extending from the wrist securing member. The finger engagement member includes a slide member extending around an exterior of the band and a plurality of finger receptacles extending from the slide member in a direction generally facing the wrist securing member. The thumb engagement member includes a first thumb receptacle, a second thumb receptacle, and a member connected to and extending between the first and second thumb receptacles.
摘要翻译：一种锻炼装置，其具有带，手腕固定构件，其连接到所述带，使得所述带从所述手腕固定构件向外延伸;以及手指接合构件，其在与所述手腕固定构件大致相对的位置处固定到所述带。手腕固定构件用于可拆卸地附接在人类手腕周围。手指接合构件向带内延伸。拇指接合构件通常在手指接合构件和手腕固定构件之间的位置处固定到带上。带具有从腕部固定构件延伸的大致刚性且大致圆形的构造。手指接合构件包括围绕带的外部延伸的滑动构件和沿着大致面向手腕固定构件的方向从滑动构件延伸的多个指状容座。拇指接合构件包括第一拇指容器，第二拇指容器和连接到第一和第二拇指插座之间并在其之间延伸的构件。

9. 发明授权

US4574362A Block mode digital signal conditioning method and apparatus 失效
标题翻译：块模数字信号调理方法及装置
公开(公告)号：US4574362A
公开(公告)日：1986-03-04
申请号：US367660
申请日：1982-04-12
申请人： Howard R. Spindel , Vincent N. Ast, Jr. , Gary L. Brown
发明人： Howard R. Spindel , Vincent N. Ast, Jr. , Gary L. Brown
IPC分类号： G06F13/38 , G06F13/42 , G06F5/00
CPC分类号： G06F13/385 , G06F13/4221
摘要： Block mode is a method of formatting data when sending it to and from the host computer. Some host computer operating systems make it difficult for the user's program to send or receive the full ASCII character set. The block mode protocol lets you send and receive messages which use the full ASCII character set (including lowercase characters and control characters), even though your host computer's operating system makes it difficult to send and receive certain ASCII characters. (Indeed, even full eight-bit binary data bytes may be sent to or from the terminal in block mode.) This is accomplished by means of a packing scheme, in which messages using the full character set are packed into character strings using a subset of that character set.Also, the block mode protocol provides error detection and automatic retransmission of bad data blocks. This lets you transfer data to and from the terminal, without errors, despite occasional noise on the communications line. Block mode is completely independent of whether or not prompt mode is used and of whether the terminal is using full duplex or half duplex communications.When in block mode, data is packed into blocks and transmitted as a unit. Each block contains an "even/odd" counter (block control byte one, bit one) which is used in an "ACK/NAK" protocol. This protocol lets the host and terminal inform each other when a block has been received incorrectly. (The block received incorrectly is then retransmitted.)
摘要翻译：块模式是将数据发送到主计算机或从主计算机发送数据时的格式化方法。一些主机操作系统使得用户的程序难以发送或接收完整的ASCII字符集。块模式协议允许您发送和接收使用完整ASCII字符集（包括小写字符和控制字符）的消息，即使您的主机操作系统难以发送和接收某些ASCII字符。（实际上，甚至可以以块模式向终端发送完整的八位二进制数据字节。）这是通过打包方案来实现的，其中使用全部字符集的消息使用子集打包到字符串中的字符集。此外，块模式协议提供错误检测和坏数据块的自动重传。这可以让您无需错误地将数据传输到终端，也可以在通信线路上偶然发生噪声。块模式完全独立于是否使用提示模式以及终端是使用全双工还是半双工通信。在块模式下，数据被打包成块并作为一个单元传输。每个块包含在“ACK / NAK”协议中使用的“偶数/奇数”计数器（块控制字节1，位1）。该协议允许主机和终端在块被错误地接收时通知对方。（接收到错误的块然后重发。

10. 发明授权

US5822555A Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer 失效
标题翻译：用于将可变长度宏指令中的指令边界与指令缓冲器对齐的方法和装置
公开(公告)号：US5822555A
公开(公告)日：1998-10-13
申请号：US716974
申请日：1996-09-20
申请人： Gary L. Brown , Donald D. Parker
发明人： Gary L. Brown , Donald D. Parker
IPC分类号： G06F9/30
CPC分类号： G06F9/30152 , G06F9/3816 , G06F9/382
摘要： A circuit and method for supplying and aligning a block of multiple variable length macro instructions to an instruction buffer. Only one cycle is required to align and rotate the block of instruction code. A last byte vector of the instruction code in the instruction buffer is scanned from the last byte in a direction from back to front, thereby saving time. Rotating begins immediately so that a next block of instruction code is available in a next cycle. The block is stored in the instruction buffer after all macroinstructions therein have been steered to the decoder.
摘要翻译：一种用于将多个可变长度宏指令的块提供和对准到指令缓冲器的电路和方法。只需一个周期来对齐和旋转指令代码块。指令缓冲器中的指令代码的最后一个字节向量从最后一个字节沿着从前到前的方向扫描，从而节省时间。立即开始旋转，以便在下一个周期中下一个指令代码块可用。在其中的所有宏指令被转向解码器之后，该块被存储在指令缓冲器中。

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