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1. 发明授权

US5668985A Decoder having a split queue system for processing intstructions in a first queue separate from their associated data processed in a second queue 失效
标题翻译：解码器具有分离队列系统，用于处理与在第二队列中处理的相关联的数据分离的第一队列中的指令
公开(公告)号：US5668985A
公开(公告)日：1997-09-16
申请号：US204992
申请日：1994-03-01
申请人： Adrian L. Carbine , Gary L. Brown , Bradley D. Hoyt , Donald D. Parker , Rajesh Kumar
发明人： Adrian L. Carbine , Gary L. Brown , Bradley D. Hoyt , Donald D. Parker , Rajesh Kumar
IPC分类号： G06F9/22 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/223 , G06F9/30145 , G06F9/3875
摘要： A split queue system for a decoder that supplies one or more micro-operations and data associated with the micro-operations. A main queue is coupled to receive one or more micro-operations from the decoder, and supply it to a next processing stage to provide a process micro-operation. A shadow queue is coupled to receive data associated with the micro-operation, in the same cycle that the micro-operation is supplied to the main queue. A control circuit is coupled to the main queue for issuing micro-operation from the main queue into the next processing stage in a first cycle, and in a second cycle issuing, the micro-operation therefrom. Also in the second cycle, the control circuit issues the data associated with the micro-operation from the shadow queue, so that the data is synchronized with its associated processed micro-operation.
摘要翻译：用于解码器的分离队列系统，其提供与微操作相关联的一个或多个微操作和数据。主队列被耦合以从解码器接收一个或多个微操作，并将其提供给下一个处理阶段以提供处理微操作。耦合影子队列以在微操作被提供给主队列的同一周期中接收与微操作相关联的数据。控制电路耦合到主队列，用于在第一周期中从主队列发出微操作到下一个处理级，并且在第二周期中从其发出微操作。同样在第二周期中，控制电路从影子队列发出与微操作相关联的数据，使得数据与其相关联的处理的微操作同步。

2. 发明授权

US5630083A Decoder for decoding multiple instructions in parallel 失效
标题翻译：解码器并行解码多条指令
公开(公告)号：US5630083A
公开(公告)日：1997-05-13
申请号：US673897
申请日：1996-07-03
申请人： Adrian L. Carbine , Gary L. Brown , Donald D. Parker
发明人： Adrian L. Carbine , Gary L. Brown , Donald D. Parker
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/28 , G06F9/30145 , G06F9/3822
摘要： A decoder for decoding multiple instructions in parallel, including a full decoder that can decode an instruction into multiple micro-operations, and a partial decoder that can decode a subset of the full instruction set.
摘要翻译：一种用于并行解码多个指令的解码器，包括可以将指令解码为多个微操作的完整解码器，以及可解码整个指令集的子集的部分解码器。

3. 发明授权

US5673427A Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue 失效
标题翻译：将从并行解码器接收的有效微操作打包到输出队列的相邻位置
公开(公告)号：US5673427A
公开(公告)日：1997-09-30
申请号：US675419
申请日：1996-07-03
申请人： Gary L. Brown , Adrian L. Carbine , Donald D. Parker
发明人： Gary L. Brown , Adrian L. Carbine , Donald D. Parker
IPC分类号： G06F9/28 , G06F9/30 , G06F9/38 , G06F9/22
CPC分类号： G06F9/30167 , G06F9/28 , G06F9/30036 , G06F9/3004 , G06F9/383
摘要： A micro-operation queue for holding a plurality of micro-operations supplied simultaneously by a decoder. A plurality of packing multiplexers are coupled to receive the plurality of micro-operations, and valid bits associated therewith, and to provide packed micro-operation data output in which the valid micro-operations are positioned in adjacent outputs, thereby removing all empty slots. A FIFO queue receives the packed data, in responsive to valid micro-operations, stores the valid micro-operations starting with the next available empty queue location. An embodiment described in which the FIFO queue includes a circular queue with a plurality of entries. In one embodiment, alignment multiplexers for the circular queue are combined with the packing multiplexers, to provide a single-level plurality of packing and aligning multiplexers that has a control system that, responsive to the valid bits of the packed data and the next available pointer of the circular queue, packs, aligns, and stores the micro-operations into the circular queue from where they can be issued.
摘要翻译：一种用于保持由解码器同时提供的多个微操作的微操作队列。耦合多个封装多路复用器以接收多个微操作以及与其相关联的有效位，并且提供压缩的微操作数据输出，其中有效微操作位于相邻的输出端，从而去除所有的空槽。 FIFO队列接收打包数据，响应于有效的微操作，存储从下一个可用空队列位置开始的有效微操作。所描述的实施例，其中FIFO队列包括具有多个条目的循环队列。在一个实施例中，用于循环队列的对准多路复用器与打包多路复用器组合，以提供具有控制系统的单级多个打包和对准多路复用器，该控制系统响应于打包数据的有效位和下一个可用指针的循环队列，将微操作打包，对齐并存储到可以从其发布的循环队列中。

4. 发明授权

US5822555A Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer 失效
标题翻译：用于将可变长度宏指令中的指令边界与指令缓冲器对齐的方法和装置
公开(公告)号：US5822555A
公开(公告)日：1998-10-13
申请号：US716974
申请日：1996-09-20
申请人： Gary L. Brown , Donald D. Parker
发明人： Gary L. Brown , Donald D. Parker
IPC分类号： G06F9/30
CPC分类号： G06F9/30152 , G06F9/3816 , G06F9/382
摘要： A circuit and method for supplying and aligning a block of multiple variable length macro instructions to an instruction buffer. Only one cycle is required to align and rotate the block of instruction code. A last byte vector of the instruction code in the instruction buffer is scanned from the last byte in a direction from back to front, thereby saving time. Rotating begins immediately so that a next block of instruction code is available in a next cycle. The block is stored in the instruction buffer after all macroinstructions therein have been steered to the decoder.
摘要翻译：一种用于将多个可变长度宏指令的块提供和对准到指令缓冲器的电路和方法。只需一个周期来对齐和旋转指令代码块。指令缓冲器中的指令代码的最后一个字节向量从最后一个字节沿着从前到前的方向扫描，从而节省时间。立即开始旋转，以便在下一个周期中下一个指令代码块可用。在其中的所有宏指令被转向解码器之后，该块被存储在指令缓冲器中。

5. 发明授权

US5600806A Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer 失效
标题翻译：用于将可变长度宏指令中的指令边界与指令缓冲器对齐的方法和装置
公开(公告)号：US5600806A
公开(公告)日：1997-02-04
申请号：US204862
申请日：1994-03-01
申请人： Gary L. Brown , Donald D. Parker
发明人： Gary L. Brown , Donald D. Parker
IPC分类号： G06F9/30 , G06F12/04
CPC分类号： G06F9/30152 , G06F9/3816 , G06F9/382
摘要： A circuit and method for supplying and aligning a block of multiple variable length macro instructions to an instruction buffer. Only one cycle is required to align and rotate the block of instruction code. A last byte vector of the instruction code in the instruction buffer is scanned from the last byte in a direction from back to front, thereby saving time. Rotating begins immediately so that a next block of instruction code is available in a next cycle. The block is stored in the instruction buffer after all macroinstructions therein have been steered to the decoder.
摘要翻译：一种用于将多个可变长度宏指令的块提供和对准到指令缓冲器的电路和方法。只需一个周期来对齐和旋转指令代码块。指令缓冲器中的指令代码的最后一个字节向量从最后一个字节沿着从前到前的方向扫描，从而节省时间。立即开始旋转，以便在下一个周期中下一个指令代码块可用。在其中的所有宏指令被转向解码器之后，该块被存储在指令缓冲器中。

6. 发明授权

US5559974A Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation 失效
标题翻译：解码器具有独立加载的微别名和宏别名寄存器，可通过一个微操作同时访问
公开(公告)号：US5559974A
公开(公告)日：1996-09-24
申请号：US459284
申请日：1995-06-02
申请人： Darrell D. Boggs , Gary L. Brown , Michael M. Hancock , Donald D. Parker
发明人： Darrell D. Boggs , Gary L. Brown , Michael M. Hancock , Donald D. Parker
IPC分类号： G06F9/30 , G06F9/35 , G06F9/38 , G06F9/22
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/35 , G06F9/3863
摘要： A decoder that includes a micro-alias register to store information from a micro-operation for use by later micro-operations in the micro-operation flow. The decoder includes one or more XLAT PLAs that produces PLA control micro-operations ("Cuops"), a microcode sequencing unit that produces microcode Cuops, and an aliasing mechanism that extracts fields and stores them in macro-alias registers. A multiplexer is provided to select the appropriate Cuop to be stored in a Cuop register. Multiple Cuops may issue each cycle. A multiplexer is coupled to select one of the Cuops and to store predetermined fields in the micro-alias register for use by subsequent Cuops. Micro-alias data and macro-alias data can be utilized simultaneously with a Cuop to form an Auop.
摘要翻译：一种解码器，其包括微型别名寄存器，用于存储来自微操作的信息以供微操作流中的后续微操作使用。解码器包括产生PLA控制微操作（“Cuops”）的一个或多个XLAT PLA，产生微代码Cuops的微代码排序单元，以及提取字段并将其存储在宏别名寄存器中的混叠机制。提供多路复用器以选择要存储在Cuop寄存器中的适当Cuop。多个Cuops可以发出每个周期。多路复用器被耦合以选择Cuops中的一个并且将预定字段存储在微别名寄存器中以供随后的Cuops使用。 Micro-alias数据和宏别名数据可以与Cuop同时使用以形成Auop。

7. 发明授权

US5586277A Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders 失效
标题翻译：包含从指令缓冲器到并行解码器的可变长度指令的固定长度字段的并行方法
公开(公告)号：US5586277A
公开(公告)日：1996-12-17
申请号：US479867
申请日：1995-06-07
申请人： Gary L. Brown , Donald D. Parker
发明人： Gary L. Brown , Donald D. Parker
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F9/3822
摘要： A circuit and method for simultaneously steering multiple aligned macroinstructions from an instruction buffer to a decoder that receives and decodes multiple macroinstructions in parallel. A first macroinstruction is supplied to a first decoder by steering a first predetermined number of bytes following the first buffer byte. A second macroinstruction is supplied by scanning a first opcode byte vector to locate a first opcode byte, and then steering a second predetermined number of bytes beginning at said first opcode to a second decoder. Operations to locate the first byte of each of the macroinstructions and to steer them to the decoders are accomplished in one cycle. If said macroinstruction cannot be decoded by said second decoder, then it is resteered to the first decoder. Steering and resteering operations continue until all complete macroinstructions within the instruction buffer have been accepted by the decoders.
摘要翻译：一种用于从指令缓冲器同时引导多个对准的宏指令到解码器的电路和方法，该解码器并行地接收和解码多个宏指令。通过转向第一缓冲区字节之后的第一预定数量的字节来将第一宏指令提供给第一解码器。通过扫描第一操作码字节向量来定位第一操作码字节，然后将从所述第一操作码开始的第二预定数量的字节转向第二解码器来提供第二宏指令。定位每个宏指令的第一个字节并将其转向解码器的操作在一个周期内完成。如果所述宏指令不能由所述第二解码器解码，则将其重新安排到第一解码器。指导缓冲区内的所有完整宏指令都被解码器接受，继续操作和重新开始操作。

8. 发明授权

US5566298A Method for state recovery during assist and restart in a decoder having an alias mechanism 失效
标题翻译：在具有别名机制的解码器中辅助和重启期间的状态恢复方法
公开(公告)号：US5566298A
公开(公告)日：1996-10-15
申请号：US204744
申请日：1994-03-01
申请人： Darrell D. Boggs , Gary L. Brown , Michael M. Hancock , Donald D. Parker , Gail M. Rupnick
发明人： Darrell D. Boggs , Gary L. Brown , Michael M. Hancock , Donald D. Parker , Gail M. Rupnick
IPC分类号： G06F9/26 , G06F9/38 , G06F11/14 , G06F11/00 , G06F11/20
CPC分类号： G06F11/1407 , G06F9/268 , G06F9/3861
摘要： A state recovery and restart method that simplifies assist handling. The recovery and restart method also handles micro-branch mispredictions. An assist sequence is executed in microcode to assist an error-causing macroinstruction. If data is required from an error-causing macroinstruction, it is fetched, decoded, and macro-alias registers are restored with macro-alias data. To recover the state of the micro-alias registers, micro-alias data from a micro-operation of the flow may be loaded into the micro-alias register. Subsequently, control returns to the Micro-operation Sequence (MS) unit to issue further error correction Control micro-operations (Cuops). In order to simplify restart, the Cuops originating from the error-causing macroinstruction supplied by the translate programmable logic arrays (XLAT PLAs) are loaded into the Cuop registers, with their valid bits unasserted. If microcode requests a restart beginning at one of the Cuops stored in the Cuop register, then the bits for that Cuop and subsequent Cuops are marked valid. Thus, the instruction can be restarted anywhere within the microcode sequence.
摘要翻译：一种简化辅助处理的状态恢复和重启方法。恢复和重新启动方法也处理微分支错误预测。在微代码中执行辅助序列以辅助引起错误的宏指令。如果需要来自导致错误的宏指令的数据，则会获取，解码和使用宏别名数据恢复宏别名寄存器。为了恢复微别名寄存器的状态，来自流程的微操作的微别名数据可以被加载到微别名寄存器中。随后，控制返回到微操作序列（MS）单元以发出进一步的纠错控制微操作（Cuops）。为了简化重新启动，由翻译可编程逻辑阵列（XLAT PLA）提供的引起误差的宏指令产生的钳位被加载到Cuop寄存器中，其有效位被置为无效。如果微码请求从Cuop寄存器中存储的一个Cuops开始重新启动，那么该Cuop和后续Cuops的位将被标记为有效。因此，可以在微代码序列内的任何地方重新启动指令。

9. 发明授权

US5581717A Decoding circuit and method providing immediate data for a micro-operation issued from a decoder 失效
标题翻译：解码电路和方法提供从解码器发出的微操作的即时数据
公开(公告)号：US5581717A
公开(公告)日：1996-12-03
申请号：US204742
申请日：1994-03-01
申请人： Darrell D. Boggs , Gary L. Brown , Donald D. Parker
发明人： Darrell D. Boggs , Gary L. Brown , Donald D. Parker
IPC分类号： G06F9/22 , G06F9/30 , G06F9/302 , G06F9/35 , G06F9/34 , G06F9/40
CPC分类号： G06F9/3001 , G06F9/223 , G06F9/30145 , G06F9/30167 , G06F9/35
摘要： Decoding circuitry and a method supplying an immediate field that is issued from a decoder. A macroinstruction is supplied to the decoding circuit, which generates a first micro-operation that includes a first aliasing field and a first immediate field. The first aliasing field indicates the source of the micro-operation that will eventually be issued from the decoder. If the source is the first immediate field, then the alias field is further examined to determine the interpretation to be placed upon the data. The data may be interpreted literally, or as an address into a constant ROM, thereby providing an ability to output wide, 32-bit immediate data from a narrower, 9-bit input addresses. Additional sources for immediate data include macro-alias registers, macro-branch information, and micro-branch information.
摘要翻译：解码电路和提供从解码器发出的立即字段的方法。宏指令被提供给解码电路，其产生包括第一混叠字段和第一立即字段的第一微操作。第一个混叠字段指示最终将从解码器发出的微操作的源。如果源是第一个立即字段，则进一步检查别名字段以确定要放置在数据上的解释。数据可以被字面地解释，或者作为一个地址到恒定的ROM中，从而提供从较窄的9位输入地址输出宽的32位立即数据的能力。即时数据的其他来源包括宏别名寄存器，宏分支信息和微分支信息。

10. 发明授权

US06880031B2 Snoop phase in a highly pipelined bus architecture 有权
标题翻译： Snoop阶段在高度流水线的总线架构中
公开(公告)号：US06880031B2
公开(公告)日：2005-04-12
申请号：US09783784
申请日：2001-02-14
申请人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
发明人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
IPC分类号： G06F13/36 , G06F13/42 , G06F13/14 , G06F12/00
CPC分类号： G06F13/4217
摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a set of snoop status interfaces, an address strobe signal interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic capable of sensing or asserting one or more of a set of snoop status signals for transaction N on the snoop status interfaces during a snoop phase to start in a bus cycle upon the later of three or more bus clock cycles of the bus clock signal after a beginning of a bus cycle of an the assertion of an address strobe signal for transaction N or two or more bus clock cycles of the bus clock signal after a beginning of a bus cycle in which a most recent snoop phase begins.
摘要翻译：可用于增强的高流水线总线架构中的总线代理。在一个实施例中，总线代理包括一组窥探状态接口，地址选通信号接口和用于总线时钟信号的总线时钟接口。该实施例的总线代理还包括总线控制器逻辑，其能够在探测阶段期间在监听阶段中在三个或更多的后期的总线周期中检测或断言用于事件N的一组窥探状态信号中的一个或多个窥探状态信号总线时钟信号的总线时钟周期在总线周期开始之后，在总线周期开始之后断言事务N的地址选通信号或总线时钟信号的两个或多个总线时钟周期，其中a 最近的窥探阶段开始了。

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