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1. 发明授权

US5862373A Pad cells for a 2/N mode clocking scheme 失效
标题翻译： Pad单元用于2 / N模式时钟方案
公开(公告)号：US5862373A
公开(公告)日：1999-01-19
申请号：US709336
申请日：1996-09-06
申请人： Chakrapani Pathikonda , Jeff Wight
发明人： Chakrapani Pathikonda , Jeff Wight
IPC分类号： G06F1/04 , G06F1/10
CPC分类号： G06F1/04
摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
摘要翻译： 2 / N模式时钟发生器，其通过使用总线时钟使能信号来产生总线时钟信号，从而选择与核心时钟信号同相和异相的总线时钟脉冲。时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

2. 发明授权

US06477674B1 Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements 有权
标题翻译：使用本地模式发生器和延迟元件进行输入/输出回路测试的方法和装置
公开(公告)号：US06477674B1
公开(公告)日：2002-11-05
申请号：US09474874
申请日：1999-12-29
申请人： Sarah E. Bates , R. Tim Frodsham , Nasser A. Kurd , Anne Meixner , David J. O'Brien , Rajay R. Pai , Mike Tripp , Jeff Wight
发明人： Sarah E. Bates , R. Tim Frodsham , Nasser A. Kurd , Anne Meixner , David J. O'Brien , Rajay R. Pai , Mike Tripp , Jeff Wight
IPC分类号： G06F1100
CPC分类号： G01R31/3187 , G01R31/31716
摘要： In one embodiment, an integrated circuit including a plurality of input/output (I/O) buffers is disclosed. The integrated circuit contains a plurality of I/O buffers. Each of the I/O buffers include an I/O test circuit that generates test pattern signals whenever the integrated circuit is operating in a loopback test mode. According to a further embodiment, the integrated circuit includes one or more programmable delay circuits coupled to the I/O buffers that permit switching state (AC) loopback timing tests to be conducted.
摘要翻译：在一个实施例中，公开了包括多个输入/输出（I / O）缓冲器的集成电路。集成电路包含多个I / O缓冲器。每个I / O缓冲器包括一个I / O测试电路，每当集成电路工作在环回测试模式时，它产生测试模式信号。根据另一实施例，集成电路包括耦合到I / O缓冲器的一个或多个可编程延迟电路，其允许进行开关状态（AC）环回定时测试。

3. 发明申请

US20060274874A1 Clock and data timing compensation for receiver 审中-公开
标题翻译：接收机的时钟和数据定时补偿
公开(公告)号：US20060274874A1
公开(公告)日：2006-12-07
申请号：US11142764
申请日：2005-06-01
申请人： Arvind Kumar , Warren Anderson , George Powley , Jeff Wight
发明人： Arvind Kumar , Warren Anderson , George Powley , Jeff Wight
IPC分类号： H04L7/04
CPC分类号： H04L7/033 , H03L7/0814 , H04L7/0025 , H04L7/0062 , H04L7/0334
摘要： According to some embodiments, a system provides acquisition of a first sample of a data signal based on a first clock signal associated with a first phase, the first sample associated with a first data eye of a clock cycle, acquisition of a second sample of the data signal based on a second clock signal associated with a second phase, the second sample associated with a second data eye of the clock cycle, determination of whether the first sample reflects expected data associated with the first data eye, control of the first phase of the first clock signal based on whether the first sample reflects the expected data associated with the first data eye, determination of whether the second sample reflects expected data associated with the second data eye, and control of the second phase of the second clock signal based on whether the second sample reflects the expected data associated with the second data eye.
摘要翻译：根据一些实施例，系统基于与第一阶段相关联的第一时钟信号提供对数据信号的第一采样的采集，第一采样与时钟周期的第一数据眼相关联，获取第一采样的第一采样基于与第二阶段相关联的第二时钟信号的数据信号，所述第二样本与所述时钟周期的第二数据眼相关联，确定所述第一样本是否反映与所述第一数据眼相关联的预期数据，所述第一时钟信号基于所述第一样本是否反映与所述第一数据眼睛相关联的预期数据，确定所述第二样本是否反映与所述第二数据眼睛相关联的预期数据，以及基于所述第二时钟信号的第二相位的控制第二样本是否反映与第二数据眼睛相关联的预期数据。

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