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1. 发明授权

US07037730B2 Capacitor with high dielectric constant materials and method of making 失效
标题翻译：具有高介电常数材料和制作方法的电容器
公开(公告)号：US07037730B2
公开(公告)日：2006-05-02
申请号：US09904112
申请日：2001-07-11
申请人： Cem Basceri , Gurtej S. Sandhu , Mark Visokay
发明人： Cem Basceri , Gurtej S. Sandhu , Mark Visokay
IPC分类号： H01L21/8242
CPC分类号： H01L28/56 , H01L27/10811
摘要： Stabilized capacitors and DRAM cells using high dielectric constant oxide dielectric materials such as Ta2O5 and BaxSr(1−x)TiO3, and methods of making such capacitors and DRAM cells are provided. A preferred method includes providing a conductive oxide electrode, depositing a first layer of a high dielectric constant oxide dielectric material on the conductive oxide electrode, oxidizing the conductive oxide electrode and the first layer of the high dielectric constant oxide dielectric material under oxidizing conditions, depositing a second layer of the high dielectric constant oxide dielectric material on the first layer of the dielectric, and depositing an upper layer electrode on the second layer of the high dielectric constant oxide dielectric material.
摘要翻译：使用高介电常数氧化物介电材料如Ta 2 O 5和Ba x Sr（1-x）的稳定电容器和DRAM单元）和提供制造这种电容器和DRAM单元的方法。优选的方法包括提供导电氧化物电极，在导电氧化物电极上沉积高介电常数氧化物介电材料的第一层，在氧化条件下氧化导电氧化物电极和高介电常数氧化物介电材料的第一层，沉积在所述电介质的第一层上的所述高介电常数氧化物电介质材料的第二层，以及在所述高介电常数氧化物介电材料的第二层上沉积上层电极。

2. 发明授权

US06833576B2 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 失效
标题翻译：含有钌和钨的层的形成方法和集成电路结构
公开(公告)号：US06833576B2
公开(公告)日：2004-12-21
申请号：US10002779
申请日：2001-10-29
申请人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
发明人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
IPC分类号： H01L27108
CPC分类号： H01L28/84 , H01L21/31637 , H01L28/55 , H01L28/65
摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.
摘要翻译：具有增加的电容的电容器包括增强的表面积（粗糙表面）导电层或与高介电常数材料相容的其它层。在一种方法中，用于这种电容器的增强表面积导电层是通过在高温或高于500℃，低压75托或更低，最理想的5托或更低的高温下处理氧化钌层形成的，产生具有至少约100埃的平均特征尺寸的纹理表面的粗糙钌层。初始氧化钌层可以通过化学气相沉积技术或溅射技术等来提供。该层可以形成在下面的导电层上。处理可以在惰性环境或还原环境中进行。可以在处理期间或之后使用供氮环境或供氮还原环境以钝化钌以改善与高介电常数电介质材料的相容性。氧化环境中的处理也可以进行以钝化粗糙层。可以使用粗糙化的钌层来形成增强表面积的导电层。所形成的增强表面积导电层可以在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。在另一种方法中，提供氮化钨层作为这种电容器的第一电极。电容器或至少氮化钨层被退火以增加电容器的电容。

3. 发明授权

US07253076B1 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 有权
标题翻译：含有钌和钨的层的形成方法和集成电路结构
公开(公告)号：US07253076B1
公开(公告)日：2007-08-07
申请号：US09590795
申请日：2000-06-08
申请人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
发明人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
IPC分类号： H01L21/20
CPC分类号： H01L28/84 , H01L21/31637 , H01L28/55 , H01L28/65
摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.
摘要翻译：具有增加的电容的电容器包括增强的表面积（粗糙表面）导电层或与高介电常数材料相容的其它层。在一种方法中，用于这种电容器的增强表面积导电层是通过在高温或高于500℃，低压75托或更低，最理想的5托或更低的高温下处理氧化钌层形成的，产生具有至少约100埃的平均特征尺寸的纹理表面的粗糙钌层。初始氧化钌层可以通过化学气相沉积技术或溅射技术等来提供。该层可以形成在下面的导电层上。处理可以在惰性环境或还原环境中进行。可以在处理期间或之后使用供氮环境或供氮还原环境以钝化钌以改善与高介电常数电介质材料的相容性。氧化环境中的处理也可以进行以钝化粗糙层。可以使用粗糙化的钌层来形成增强表面积的导电层。所形成的增强表面积导电层可以在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。在另一种方法中，提供氮化钨层作为这种电容器的第一电极。电容器或至少氮化钨层被退火以增加电容器的电容。

4. 发明授权

US06596583B2 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 有权
公开(公告)号：US06596583B2
公开(公告)日：2003-07-22
申请号：US10002906
申请日：2001-10-29
申请人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
发明人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L21/31637 , H01L28/55 , H01L28/65
摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

5. 发明授权

US08207563B2 Integrated circuitry 有权
标题翻译：集成电路
公开(公告)号：US08207563B2
公开(公告)日：2012-06-26
申请号：US11638931
申请日：2006-12-13
申请人： Cem Basceri , Gurtej S. Sandhu
发明人： Cem Basceri , Gurtej S. Sandhu
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid pervious material. A capacitor dielectric material is deposited over the capacitor electrodes through the fluid pervious material of the retaining structure effective to deposit capacitor dielectric material over portions of the sidewalls received below the retaining structure. Capacitor electrode material is deposited over the capacitor dielectric material through the fluid pervious material of the retaining structure effective to deposit capacitor electrode material over at least some of the capacitor dielectric material received below the retaining structure. Integrated circuitry independent of method of fabrication is also contemplated.
摘要翻译：形成多个电容器的方法包括提供包括侧壁的多个电容器电极。多个电容器电极至少部分地由与侧壁接合的保持结构支撑，保持结构包括透液材料。电容器电介质材料沉积在电容器电极上，通过保持结构的流体可渗透材料，其有效地将电容器电介质材料沉积在容纳在保持结构下方的侧壁的部分上。电容器电极材料通过保持结构的流体可透过材料沉积在电容器介电材料上，有效地将电容器电极材料沉积在容纳在保持结构下方的电容器电介质材料的至少一些之上。还考虑了与制造方法无关的集成电路。

6. 发明申请

US20120120549A1 Mixed Composition Interface Layer and Method of Forming 审中-公开
标题翻译：混合组合界面层和成型方法
公开(公告)号：US20120120549A1
公开(公告)日：2012-05-17
申请号：US13293778
申请日：2011-11-10
申请人： Cem Basceri , Gurtej S. Sandhu
发明人： Cem Basceri , Gurtej S. Sandhu
IPC分类号： H01G9/00
CPC分类号： H01L21/0228 , C23C16/029 , C23C16/18 , C23C16/405 , C23C16/45525 , H01L21/02183 , H01L21/28562 , H01L21/31604 , H01L21/31683 , H01L28/40 , H01L28/60 , Y10T428/24917 , Y10T428/24926
摘要： An interface forming method includes forming a first layer containing a first chemical element and chemisorbing on the first layer an interface layer containing at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element. A second layer comprising the second chemical element can be formed on the interface layer. The first layer might not substantially contain the second chemical element, the second layer might not substantially contain the first chemical element, or both. An apparatus can include a first layer containing a first chemical element, an interface layer chemisorbed on the first layer, and a second layer containing a second element on the interface layer. The interface layer can contain at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element.
摘要翻译：界面形成方法包括在第一层上形成含有第一化学元素和化学吸附的第一层，所述界面层含有与第一化学元素不同的第二化学元素混合的第一化学元素的至少一个单层。包含第二化学元素的第二层可以形成在界面层上。第一层可能基本上不包含第二化学元素，第二层可能基本上不含有第一化学元素，或两者都不包含。装置可以包括含有第一化学元素的第一层，在第一层上化学吸附的界面层和在界面层上含有第二元素的第二层。界面层可以包含与第一化学元素不同的第二化学元素混合的第一化学元素的至少一个单层。

7. 再颁专利

USRE43025E1 Mixed composition interface layer and method of forming 有权
标题翻译：混合组成界面层和成型方法
公开(公告)号：USRE43025E1
公开(公告)日：2011-12-13
申请号：US12566533
申请日：2009-09-24
申请人： Cem Basceri , Gurtej S. Sandhu
发明人： Cem Basceri , Gurtej S. Sandhu
IPC分类号： B32B9/00
CPC分类号： H01L21/0228 , C23C16/029 , C23C16/18 , C23C16/405 , C23C16/45525 , H01L21/02183 , H01L21/28562 , H01L21/31604 , H01L21/31683 , H01L28/40 , H01L28/60 , Y10T29/417 , Y10T428/24917 , Y10T428/24926
摘要： An interface forming method includes forming a first layer containing a first chemical element and chemisorbing on the first layer an interface layer containing at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element. A second layer comprising the second chemical element can be formed on the interface layer. The first layer might not substantially contain the second chemical element, the second layer might not substantially contain the first chemical element, or both. An apparatus can include a first layer containing a first chemical element, an interface layer chemisorbed on the first layer, and a second layer containing a second element on the interface layer. The interface layer can contain at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element.
摘要翻译：界面形成方法包括在第一层上形成含有第一化学元素和化学吸附的第一层，所述界面层含有与第一化学元素不同的第二化学元素混合的第一化学元素的至少一个单层。包含第二化学元素的第二层可以形成在界面层上。第一层可能基本上不包含第二化学元素，第二层可能基本上不含有第一化学元素，或两者都不包含。装置可以包括含有第一化学元素的第一层，在第一层上化学吸附的界面层和在界面层上含有第二元素的第二层。界面层可以包含与第一化学元素不同的第二化学元素混合的第一化学元素的至少一个单层。

8. 发明授权

US07633116B2 One-transistor composite-gate memory 有权
标题翻译：单晶体管复合栅极存储器
公开(公告)号：US07633116B2
公开(公告)日：2009-12-15
申请号：US11782442
申请日：2007-07-24
申请人： Cem Basceri , Gurtej S. Sandhu
发明人： Cem Basceri , Gurtej S. Sandhu
IPC分类号： H01L29/792
CPC分类号： G11C11/5671 , G11C8/12 , G11C16/0416 , G11C16/0466 , H01L29/513 , H01L29/792
摘要： One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.
摘要翻译：单晶体管存储器件通过操纵场效应晶体管（FET）的俘获层内的氧空位来促进非易失性数据存储，从而提供晶体管的阈值电压的控制和变化。可以为各种阈值电压分配数据值，提供将一个或多个位数据存储在单个存储器单元中的能力。为了控制阈值电压，可以通过在空位内捕获电子来操纵氧空位，从空位释放被俘获的电子，移动捕获层内的空位并湮灭空位。

9. 发明授权

US07585728B2 Methods of programming memory cells using manipulation of oxygen vacancies 有权
标题翻译：使用氧空位操纵来编程记忆体的方法
公开(公告)号：US07585728B2
公开(公告)日：2009-09-08
申请号：US11837149
申请日：2007-08-10
申请人： Cem Basceri , Gurtej S. Sandhu
发明人： Cem Basceri , Gurtej S. Sandhu
IPC分类号： H01L21/336
CPC分类号： G11C11/5671 , G11C8/12 , G11C16/0416 , G11C16/0466 , H01L29/513 , H01L29/792
摘要： One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.
摘要翻译：单晶体管存储器件通过操纵场效应晶体管（FET）的俘获层内的氧空位来促进非易失性数据存储，从而提供晶体管的阈值电压的控制和变化。可以为各种阈值电压分配数据值，提供将一个或多个位数据存储在单个存储器单元中的能力。为了控制阈值电压，可以通过在空位内捕获电子来操纵氧空位，从空位释放被俘获的电子，移动捕获层内的空位并湮灭空位。

10. 发明授权

US07517758B2 Method of forming a vertical transistor 有权
标题翻译：形成垂直晶体管的方法
公开(公告)号：US07517758B2
公开(公告)日：2009-04-14
申请号：US11256430
申请日：2005-10-20
申请人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
发明人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
IPC分类号： H01L21/336
CPC分类号： H01L29/66787 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L29/66553 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成外延含硅材料的方法和形成垂直晶体管的方法。在一个实施方案中，形成外延含硅材料的方法包括提供包括单晶材料的衬底。单晶材料的第一部分向外暴露，而单晶材料的第二部分被掩蔽。第一含硅层从第一部分的暴露的单晶材料而不是被掩蔽的第二部分的单晶材料外延生长。在生长第一含硅层之后，单晶材料的第二部分被未掩蔽。然后从第一含硅层和第二部分的未掩模的单晶材料外延生长第二含硅层。考虑了其他方面和实现。

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