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    • 6. 发明授权
    • Adaptive data compression system with systolic string matching logic
    • 具有收缩字符串匹配逻辑的自适应数据压缩系统
    • US5532693A
    • 1996-07-02
    • US259760
    • 1994-06-13
    • Kel D. WintersPatrick A. OwsleyCatherine A. FrenchRobert M. BodePeter S. Feeley
    • Kel D. WintersPatrick A. OwsleyCatherine A. FrenchRobert M. BodePeter S. Feeley
    • G06F7/02G06T9/00H03K3/037H03K3/356H03M7/30
    • G06F7/02G06T9/005H03K3/037H03K3/356156H03M7/3086
    • An adaptive lossless data compression system with systolic string matching logic performs compression and decompression at the maximum rate of one symbol per clock cycle. The adaptive data compression system uses an improvement of the LZ1 algorithm. A content addressable memory (CAM) is used to store the last n input symbols. The CAM is stationary, stored data is not shifted throughout the CAM, but rather the CAM is used as a circular queue controlled by a Write Address Pointer Counter (WREN). During a compression operation, a new input symbol may be written to the CAM on each clock cycle, while simultaneously the rest of the CAM is searched for the input symbol. Associated with each word of the CAM array is a String Match State Machine (SMSM) and, an address logic module (ALM). These modules detect the occurrence of strings stored in the CAM array that match the current input string and report the address of the longest matching string nearest to the Write Address Pointer. The SMSM modules constitute a systolic logic array, where state information is shifted synchronously in the direction of the Write Address Pointer. The strings are represented by a string code which includes a length value, representing the length of the string, and a position value, representing the position in the CAM of the beginning of the string. During a decompression operation, the single symbols and string codes are input to the system. The symbols are stored in the CAM and the control logic outputs the decompressed data symbols using the stored data and the string codes.
    • 具有收缩串匹配逻辑的自适应无损数据压缩系统以每个时钟周期的一个符号的最大速率执行压缩和解压缩。 自适应数据压缩系统使用LZ1算法的改进。 内容可寻址存储器(CAM)用于存储最后n个输入符号。 CAM是静止的,存储的数据不会在整个CAM中移动,而是CAM被用作由写地址指针计数器(WREN)控制的循环队列。 在压缩操作期间,可以在每个时钟周期将新的输入符号写入CAM,同时搜索CAM的其余部分来输入符号。 与CAM阵列的每个单词相关联的是字符串匹配状态机(SMSM)和地址逻辑模块(ALM)。 这些模块检测存储在CAM阵列中与当前输入字符串相匹配的字符串的出现,并报告最接近写入地址指针的最长匹配字符串的地址。 SMSM模块构成收缩逻辑阵列,其中状态信息在写地址指针的方向上同步移位。 字符串由字符串代码表示,字符串代码包括表示字符串长度的长度值和表示字符串开头的CAM中的位置的位置值。 在解压缩操作期间,单个符号和字符串代码被输入到系统。 符号存储在CAM中,控制逻辑使用存储的数据和字符串代码来输出解压缩的数据符号。
    • 9. 发明授权
    • Single-stack implementation of a Reed-Solomon encoder/decoder
    • Reed-Solomon编码器/解码器的单栈实现
    • US5396502A
    • 1995-03-07
    • US911153
    • 1992-07-09
    • Patrick A. OwsleyTorkjell BergeCatherine A. French
    • Patrick A. OwsleyTorkjell BergeCatherine A. French
    • G06F11/10G06F7/72H03M13/00H03M13/01H03M13/15
    • H03M13/15G06F7/726
    • The present invention is for a Error Correction Unit (ECU) that uses a single stack architecture for the generation, reduction and evaluation of the polynomials involved in the correction of a Reed-Solomon code. The circuit uses the same hardware to generate the syndromes, reduce the .OMEGA.(x) and .LAMBDA.(x) polynomials and evaluate the .OMEGA.(x) and .LAMBDA.(x) polynomials. Some of the specifics involved in calculating and reducing the polynomials mentioned above are novel as well. First, the implementation of the general Galois field multiplier is new and faster than previous implementations. Second, the circuit for implementing the Galois field inverse function has not appeared in prior art designs. Third, a novel method of generating the .OMEGA.(x) and .LAMBDA.(x) polynomials (including alignment of these polynomials prior to evaluation) is utilized. Fourth, corrections are performed in the same order as they are received using a premultiplication step prior to evaluation. Fifth, a novel method of implementing flags for uncorrectable errors is used. Sixth, the ECU is data driven in that nothing happens if no data is present. Finally, interleaved data is handled internally to the chip.
    • 本发明涉及一种误差校正单元(ECU),该纠错单元使用单个堆叠架构来生成,减少和评估涉及Reed-Solomon码校正的多项式。 该电路使用相同的硬件来产生综合征,减少OMEGA(x)和LAMBDA(x)多项式,并评估OMEGA(x)和LAMBDA(x)多项式。 计算和减少上述多项式的一些细节也是新颖的。 首先,一般Galois域乘法器的实现是比以前的实现新的和更快的。 其次,用于实现伽罗瓦域反函数的电路在现有技术设计中没有出现。 第三,利用生成OMEGA(x)和LAMBDA(x)多项式(包括评估之前这些多项式的对齐)的新方法。 第四,在评估之前使用预乘步骤以与它们接收的顺序相同的顺序进行校正。 第五,使用了一种用于实现不可校正错误的标志的新方法。 第六,ECU是数据驱动的,因为没有数据存在,没有任何反应。 最后,交织数据在芯片内部处理。