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1. 发明授权

US5396502A Single-stack implementation of a Reed-Solomon encoder/decoder 失效
标题翻译： Reed-Solomon编码器/解码器的单栈实现
公开(公告)号：US5396502A
公开(公告)日：1995-03-07
申请号：US911153
申请日：1992-07-09
申请人： Patrick A. Owsley , Torkjell Berge , Catherine A. French
发明人： Patrick A. Owsley , Torkjell Berge , Catherine A. French
IPC分类号： G06F11/10 , G06F7/72 , H03M13/00 , H03M13/01 , H03M13/15
CPC分类号： H03M13/15 , G06F7/726
摘要： The present invention is for a Error Correction Unit (ECU) that uses a single stack architecture for the generation, reduction and evaluation of the polynomials involved in the correction of a Reed-Solomon code. The circuit uses the same hardware to generate the syndromes, reduce the .OMEGA.(x) and .LAMBDA.(x) polynomials and evaluate the .OMEGA.(x) and .LAMBDA.(x) polynomials. Some of the specifics involved in calculating and reducing the polynomials mentioned above are novel as well. First, the implementation of the general Galois field multiplier is new and faster than previous implementations. Second, the circuit for implementing the Galois field inverse function has not appeared in prior art designs. Third, a novel method of generating the .OMEGA.(x) and .LAMBDA.(x) polynomials (including alignment of these polynomials prior to evaluation) is utilized. Fourth, corrections are performed in the same order as they are received using a premultiplication step prior to evaluation. Fifth, a novel method of implementing flags for uncorrectable errors is used. Sixth, the ECU is data driven in that nothing happens if no data is present. Finally, interleaved data is handled internally to the chip.
摘要翻译：本发明涉及一种误差校正单元（ECU），该纠错单元使用单个堆叠架构来生成，减少和评估涉及Reed-Solomon码校正的多项式。该电路使用相同的硬件来产生综合征，减少OMEGA（x）和LAMBDA（x）多项式，并评估OMEGA（x）和LAMBDA（x）多项式。计算和减少上述多项式的一些细节也是新颖的。首先，一般Galois域乘法器的实现是比以前的实现新的和更快的。其次，用于实现伽罗瓦域反函数的电路在现有技术设计中没有出现。第三，利用生成OMEGA（x）和LAMBDA（x）多项式（包括评估之前这些多项式的对齐）的新方法。第四，在评估之前使用预乘步骤以与它们接收的顺序相同的顺序进行校正。第五，使用了一种用于实现不可校正错误的标志的新方法。第六，ECU是数据驱动的，因为没有数据存在，没有任何反应。最后，交织数据在芯片内部处理。

2. 发明授权

US5822341A Multiport RAM for use within a viterbi decoder 失效
标题翻译：多端口RAM用于维特比解码器
公开(公告)号：US5822341A
公开(公告)日：1998-10-13
申请号：US418661
申请日：1995-04-06
申请人： Paul Winterrowd , Torkjell Berge
发明人： Paul Winterrowd , Torkjell Berge
IPC分类号： G11C8/16 , H03M13/41 , G06F11/10
CPC分类号： H03M13/4169 , G11C8/16 , H03M13/41
摘要： A memory block structure for use within a viterbi decoder includes multiple dual port RAMs configured as multiport RAMs. The memory block structure is configured to allow a one-word write operation and an N-word read operation during a single clock cycle in order to achieve one decoded output symbol per clock period using the viterbi algorithm. By using dual port RAMs, a more densely packed and less expensive memory block structure is achieved. An encoded stream of input symbols are input to the viterbi decoder and written to the memory block structure one word at a time. Once X+Y bits have been written to the memory block structure, the decoder will then read N words from the memory block structure, simultaneously, reading back through X+Y words and outputting Y bits N at a time at the end of the trace back through memory. This process is repeated once the next Y words have been written to the memory block 22, with X+Y words being traced back through and the appropriate Y bits being output, until the entire encoded stream of input symbols has been decoded.
摘要翻译：在维特比解码器中使用的存储器块结构包括配置为多端口RAM的多个双端口RAM。存储器块结构被配置为在单个时钟周期期间允许一字写入操作和N字读操作，以便使用维特比算法在每个时钟周期内实现一个解码的输出符号。通过使用双端口RAM，实现了更密集封装和更便宜的存储器块结构。将输入符号的编码流输入到维特比解码器，并一次写入存储器块结构一个字。一旦X + Y位被写入存储器块结构，解码器将从存储器块结构中读取N个字，同时通过X + Y个字读回并在跟踪结束时一次输出Y个位N 回忆一下一旦已经将下一个Y字写入存储器块22，将X + Y个字追溯到正在输出的适当的Y位，直到输入符号的整个编码流被解码为止，这一过程被重复。

3. 发明授权

US06704901B1 Runtime programmable Reed-Solomon decoder 失效
标题翻译：运行时可编程Reed-Solomon解码器
公开(公告)号：US06704901B1
公开(公告)日：2004-03-09
申请号：US09613471
申请日：2000-07-11
申请人： Torkjell Berge , Aaron James Brennan
发明人： Torkjell Berge , Aaron James Brennan
IPC分类号： H03M1300
CPC分类号： H03M13/158
摘要： A runtime programable RS decoder that can operate on multiple pieces of data during one clock cycle in order to generate, reduce, and evaluate polynomials involved in the decoding of an RS code, and which allows a user to choose the RS code after the circuit has been implemented.
摘要翻译：一种可运行时可编程的RS解码器，其可以在一个时钟周期内对多条数据进行操作，以便生成，减少和评估涉及RS码解码的多项式，并且允许用户在电路具有RS码之后选择RS码已实施。

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