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1. 发明授权

US4272829A Reconfigurable register and logic circuitry device for selective connection to external buses 失效
标题翻译：可重配置寄存器和逻辑电路设备，用于选择性连接到外部总线
公开(公告)号：US4272829A
公开(公告)日：1981-06-09
申请号：US865457
申请日：1977-12-29
申请人： Carson T. Schmidt , William P. Ward , Rocky M. Y. Young
发明人： Carson T. Schmidt , William P. Ward , Rocky M. Y. Young
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/405
摘要： A register circuit capable of use in various components of a computer. The register circuit includes two registers and logic circuitry that enables plural data buses to be selectively connected in various configurations to the data inputs and outputs of the registers. In an embodiment showing the register circuit constructed using emitter coupled logic, a clocking circuit generates clocking signals for selecting the data buses to be connected to the input of each register. Each register comprises plural master-slave flip-flops which receive the clocking signals from the clocking circuit and operatively connect the flip-flops to the selected bus or buses in response to such signals.
摘要翻译：一种能够用于计算机的各种组件的寄存器电路。寄存器电路包括两个寄存器和逻辑电路，其使多个数据总线能够以各种配置选择性地连接到寄存器的数据输入和输出。在示出使用发射极耦合逻辑构造的寄存器电路的实施例中，时钟电路产生用于选择要连接到每个寄存器的输入的数据总线的时钟信号。每个寄存器包括多个主从触发器，其接收来自时钟电路的时钟信号，并且响应于这些信号将触发器可操作地连接到所选择的总线或总线。

2. 发明授权

US5001625A Bus structure for overlapped data transfer 失效
标题翻译：用于重叠数据传输的总线结构
公开(公告)号：US5001625A
公开(公告)日：1991-03-19
申请号：US173212
申请日：1988-03-24
申请人： James H. Thomas , Royston L. Smith , William P. Ward
发明人： James H. Thomas , Royston L. Smith , William P. Ward
IPC分类号： G06F13/40
CPC分类号： G06F13/4063
摘要： An improved system bus structure for versatile use in various digital computer architecture configurations, particularly those of mini-supercomputers, and, designed to support high speed, high reliability, parallel processing of bi-directional signal transfers in a multi-port and multiple central processor unit (CPU) communication environment as between system bus units or devices. The system bus structure may be sized for a compact encasement and may carry as many as 129 simultaneous signals to and from various units connected to it. The system bus structure includes enabling structure for a centralized arbitration system, a centralized clock and synchronized transfer system, a centralized transfer monitor, a centralized parity error assessor and signalling system including transfer termination, and, a memory/inter-system inhibit system.
摘要翻译：一种改进的系统总线结构，用于各种数字计算机体系结构（特别是小型超级计算机的配置）中的多功能应用，并且被设计为支持多端口和多个中央处理器中的双向信号传输的高速，高可靠性的并行处理单位（CPU）通信环境在系统总线单元或设备之间。系统总线结构的尺寸可以用于紧凑的外壳，并且可以将多达129个同时的信号传送到连接到它的各个单元和从多个单元传送。系统总线结构包括集中仲裁系统的启用结构，集中式时钟和同步传输系统，集中式传输监视器，集中式奇偶校验错误评估器和包括传输终止的信令系统，以及存储器/系统间禁止系统。

3. 发明授权

US4148099A Memory device having a minimum number of pins 失效
标题翻译：存储器件具有最小数量的引脚
公开(公告)号：US4148099A
公开(公告)日：1979-04-03
申请号：US895329
申请日：1978-04-11
申请人： Donald K. Lauffer , William P. Ward
发明人： Donald K. Lauffer , William P. Ward
IPC分类号： G11C11/41 , G06F13/42 , G11C5/00 , G11C5/06 , G11C7/00 , G11C11/401 , G11C11/413 , G11C13/00
CPC分类号： G06F13/4243 , G11C5/00 , G11C5/066
摘要： A circuit for reducing the number of external pins or terminals on a memory device includes a counter circuit which periodically causes the signal on a first external pin to be provided to the power terminal of an internal power supply within the memory device and, at the same time, causes the ground level signal on a second external pin to be provided to the ground terminal of the internal power supply. At other times during the receipt of signals on the two external pins, the signal on the first pin provides both memory select and clocking functions and the signal on the second pin provides memory mode select, address, and data input and output functions.
摘要翻译：用于减少存储器件上的外部引脚或端子数量的PG电路包括一个周期性地将第一外部引脚上的信号提供给存储器件内的内部电源的电源端口的计数器电路，以及同时，将第二外部引脚上的接地电平信号提供给内部电源的接地端子。在接收两个外部引脚上的信号的其他时间，第一个引脚上的信号提供存储器选择和时钟功能，第二个引脚上的信号提供存储模式选择，地址和数据输入和输出功能。

4. 发明授权

US06868486B1 Providing multiple memory controllers on a memory bus 有权
标题翻译：在内存总线上提供多个内存控制器
公开(公告)号：US06868486B1
公开(公告)日：2005-03-15
申请号：US09651229
申请日：2000-08-25
申请人： William P. Ward
发明人： William P. Ward
IPC分类号： G06F12/08 , G06F13/16 , G06F12/06
CPC分类号： G06F13/1605 , G06F12/0831
摘要： A system comprises a plurality of memory controllers connected to a memory bus. Each memory controller is able to generate memory requests on the memory bus according to a predetermined priority scheme. One priority scheme is a time slot priority scheme, and another priority scheme is a request-select priority scheme. The plurality of memory controllers are able to monitor memory requests generated by another memory controller in performing memory-related actions, such as memory requests (read or write), read-modify-write transaction, and cache coherency actions. In one arrangement, the memory bus is a Rambus channel.
摘要翻译：系统包括连接到存储器总线的多个存储器控制器。每个存储器控制器能够根据预定的优先级方案在存储器总线上产生存储器请求。一个优先方案是时隙优先方案，另一优先方案是请求优先方案。多个存储器控制器能够监视由另一存储器控制器执行存储器相关动作（诸如存储器请求（读或写），读 - 修改 - 写事务和高速缓存一致性动作）所产生的存储器请求。在一种布置中，存储器总线是Rambus通道。

5. 发明授权

US4202046A Data storage system for storing multilevel signals 失效
标题翻译：用于存储多电平信号的数据存储系统
公开(公告)号：US4202046A
公开(公告)日：1980-05-06
申请号：US939021
申请日：1978-09-01
申请人： William P. Ward
发明人： William P. Ward
IPC分类号： G11C11/34 , G11C19/00 , G11C19/28 , G11C19/36 , G11C27/00 , G11C27/04 , G11C7/06
CPC分类号： G11C19/36 , G11C19/285
摘要： A data storage system for storing multilevel, non-binary data includes a charge coupled device (CCD) shift register and a detection circuit for detecting the data level represented by the charge or signal within each cell location of the CCD shift register. The detection circuit includes a sense amplifier for comparing the signals from two adjacent cell locations, with one signal representing a known data level. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors cause the output of an incrementing digital-to-analog converter to be added to one of the signals prior to comparison. The output of the sense amplifier is provided to a flip-flop, which controls the switching transistors. The outputs of the sense amplifier and flip-flop are connected to an EXCLUSIVE NOR gate, whose output enables an up/down counter, which in turn provides the detected data level.
摘要翻译：用于存储多电平，非二进制数据的数据存储系统包括电荷耦合器件（CCD）移位寄存器和用于检测由CCD移位寄存器的每个单元位置内的电荷或信号表示的数据电平的检测电路。检测电路包括读出放大器，用于比较来自两个相邻单元位置的信号，以及一个表示已知数据电平的信号。相邻单元位置的比较补偿了移位期间的信号损耗，因为相邻单元位置所经历的损耗几乎相同。开关晶体管使得在比较之前将递增的数模转换器的输出添加到一个信号。读出放大器的输出被提供给控制开关晶体管的触发器。读出放大器和触发器的输出端连接到EXCLUSIVE或非门，其输出使能上/下计数器，进而提供检测到的数据电平。

6. 发明授权

US4145760A Memory device having a reduced number of pins 失效
标题翻译：具有减少的引脚数的存储器件
公开(公告)号：US4145760A
公开(公告)日：1979-03-20
申请号：US895328
申请日：1978-04-11
申请人： William P. Ward , Donald K. Lauffer
发明人： William P. Ward , Donald K. Lauffer
IPC分类号： G11C11/41 , G06F13/42 , G11C5/00 , G11C5/06 , G11C7/00 , G11C11/401 , G11C11/413 , G11C19/28 , H03K17/30 , G11C13/00
CPC分类号： G11C19/282 , G06F13/4243 , G11C19/287 , G11C5/00 , G11C5/066 , H03K17/302 , Y02B60/1228 , Y02B60/1235
摘要： A memory device includes a circuit for reducing the number of pins or external terminals on the memory device. A threshold detector within the circuit detects the difference in voltage between signals applied at two external pins. A clocking signal at one pin provides, in addition to a synchronizing function, a memory device select function, and a signal at the other pin provides memory mode select as well as memory address, data input and data output functions. Switching transistors controlled by the output of the threshold detector connect the external pins to the power and ground terminals of an internal power supply so that the signals at the two external pins also provide the power and ground signals to the memory device.
摘要翻译： {PG，1 A存储器件包括用于减少存储器件上的引脚数量或外部端子的电路。电路内的阈值检测器检测两个外部引脚之间施加的信号之间的电压差。一个引脚上的时钟信号除了同步功能外还提供存储器件选择功能，另一个引脚上的信号提供存储器模式选择以及存储器地址，数据输入和数据输出功能。由阈值检测器的输出控制的开关晶体管将外部引脚连接到内部电源的电源和接地端子，使得两个外部引脚上的信号也向存储器件提供电源和接地信号。

7. 发明授权

US4953079A Cache memory address modifier for dynamic alteration of cache block fetch sequence 失效
标题翻译：高速缓存存储器地址修改器用于高速缓存块提取序列的动态改变
公开(公告)号：US4953079A
公开(公告)日：1990-08-28
申请号：US173406
申请日：1988-03-24
申请人： William P. Ward , Douglas R. Beard
发明人： William P. Ward , Douglas R. Beard
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： A cache memory includes an address modification circuit for operation during a cache block fetch sequence. The address modification circuit is connected to a polling circuit which receives a first word address from other portions of the cache memory connected to an instruction unit. The polling circuit tests whether a memory module storing the first word is free to make a data return transfer to the cache memory. When the memory module indicates that it is inhibited from making the data return to the cache memory, the address modification circuit selects in order of priority the next word in a cache block to be fetched and polls a memory module storing the next word. Word address selection and polling continues until a free memory module responds or until all words in the cache block have been fetched from main memory.
摘要翻译：高速缓存存储器包括用于在高速缓存块获取序列期间操作的地址修改电路。地址修改电路连接到轮询电路，该轮询电路从连接到指令单元的高速缓冲存储器的其他部分接收第一字地址。轮询电路测试存储第一个字的存储器模块是否可以将数据返回传输到高速缓冲存储器。当存储器模块指示其被禁止使数据返回到高速缓冲存储器时，地址修改电路按优先顺序选择要获取的高速缓存块中的下一个字，并轮询存储下一个字的存储器模块。字地址选择和轮询继续进行，直到可用内存模块响应或直到高速缓存块中的所有单词都已从主内存中取出。

8. 发明授权

US4183095A High density memory device 失效
标题翻译：高密度存储器件
公开(公告)号：US4183095A
公开(公告)日：1980-01-08
申请号：US939297
申请日：1978-09-01
申请人： William P. Ward
发明人： William P. Ward
IPC分类号： G11C7/00 , G06F13/42 , G11C7/22 , G11C11/34 , G11C11/401 , G11C11/409 , G11C11/414 , G11C27/00 , G11C13/00 , G11C11/40
CPC分类号： G11C11/414 , G06F13/4243 , G11C11/409 , G11C7/22 , Y02B60/1228 , Y02B60/1235
摘要： A high density memory system is formed by reducing the number of electrical conductors that are needed to connect individual memory devices into an operable memory system. The reduction is accomplished by serially reading and writing data from and into selected memory elements on one function conductor while eliminating the need for additional control conductors by causing the state of the signal on a clock conductor as compared to the state of the signal on the function conductor at selected times to control the operating mode of the memory system.
摘要翻译：通过减少将各个存储器件连接到可操作的存储器系统中所需的电导体的数量来形成高密度存储器系统。通过在一个功能导体上串行地读取和写入数据到选定的存储器元件中来实现该减少，而与功能上的信号的状态相比，通过使时钟导体上的信号的状态不再需要额外的控制导体来实现导体选择时间来控制存储系统的工作模式。

9. 发明授权

US4135242A Method and processor having bit-addressable scratch pad memory 失效
标题翻译：具有位寻址的临时存储器的方法和处理器
公开(公告)号：US4135242A
公开(公告)日：1979-01-16
申请号：US849048
申请日：1977-11-07
申请人： William P. Ward , George B. Gillow
发明人： William P. Ward , George B. Gillow
IPC分类号： G06F9/22 , G06F9/06 , G06F9/34 , G06F9/35 , G06F9/38 , G06F12/04 , G06F12/08 , G06F13/00
CPC分类号： G06F9/35 , G06F12/04 , G06F9/34 , G06F9/383
摘要： A microprogrammed processor having a bit-addressable scratch pad memory with variable length operands and a method of operation which increase processor operating speed, permit use of simpler interpretive firmware, and require a reduced amount of firmware memory than prior microprogrammed processors. Microinstructions each including a six bit op code field and first and second five bit address fields are stored in a high speed firmware memory. The two address fields are transferred to address inputs of a dual port descriptor memory which stores descriptors. Two descriptors are simultaneously fetched from locations of the descriptor memory determined by the first and second address fields of the microinstruction. Each descriptor includes an address field which defines a location of the least significant bit of an operand in the scratch pad memory and a length field which defines the length of that operand. Two operands or partial operands are fetched from the scratch pad memory and transferred to a rotator circuit which automatically aligns the fetched operand to an arithmetic and logic unit which performs iterative and fractional operations. The disclosed system and method permit interpretation of virtual instructions without utilizing additional firmware subroutines to accomplish shifting or masking of variable length operands or to perform iterative operations or carry safe operations involving the operands to align them with fixed width hardware of the processor.
摘要翻译：一种微程序处理器，具有可位长度操作数的可位址暂存器存储器和提高处理器操作速度的操作方法，允许使用更简单的解释性固件，并且需要比先前的微程序处理器更少量的固件存储器。每个包括六位操作码字段和第一和第二五位地址字段的微指令都存储在高速固件存储器中。两个地址字段被传送到存储描述符的双端口描述符存储器的地址输入。从由微指令的第一和第二地址字段确定的描述符存储器的位置同时提取两个描述符。每个描述符包括一个地址字段，其定义了临时存储器中操作数的最低有效位的位置以及定义该操作数的长度的长度字段。两个操作数或部分操作数从暂存器存储器中取出并传送到旋转电路，该电路自动对准所获取的操作数与执行迭代和分数运算的算术和逻辑单元。所公开的系统和方法允许对虚拟指令的解释，而不利用附加的固件子程序来实现可变长度操作数的移位或掩蔽，或执行迭代操作或携带涉及操作数的安全操作，以使它们与处理器的固定宽度硬件对齐。

10. 发明申请

US20120111153A1 Combined Corked Bottle Opener and Fluid Aerator 失效
标题翻译：组合软木开瓶器和流体充气机
公开(公告)号：US20120111153A1
公开(公告)日：2012-05-10
申请号：US13289584
申请日：2011-11-04
申请人： William P. Ward
发明人： William P. Ward
IPC分类号： B67B7/04
CPC分类号： B67B7/0441 , B67B7/04
摘要： An apparatus used for a corked bottle opening and fluid aeration device. It is comprised of a vertical holder with features to receive and guide the bottle and with features to permit and direct fluid flow for aeration; a cork-engaging member with a handle and corkscrew; a fluid receiving section; and a means for connecting the apparatus to the atmosphere. Preferably the features divide the sections by a stop, by a cone shape, and by a shoulder. The apparatus engages the corkscrew to the holder when used as a bottle opener and the apparatus restricts fluid flow enabling a venturi effect when used as an aerator. The apparatus allows a full hand grip on holder and bottle to ease removal of a cork from the bottle.
摘要翻译：用于软木塞瓶和流体曝气装置的装置。它包括一个垂直保持器，具有接收和引导瓶子的特征，并具有允许和引导流体流动通风的特征; 具有把手和开瓶器的软木接合构件; 流体接收部; 以及用于将设备连接到大气的装置。优选地，这些特征通过止动件，锥形形状和肩部将部分分开。当用作开瓶器时，该装置将开瓶器接合到支架上，并且当用作充气器时，该装置限制能够实现文丘里效应的流体流动。该装置允许在保持器和瓶子上的全手抓握以方便从瓶中取出软木塞。

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