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1. 发明授权

US06391668B1 Method of determining a trap density of a semiconductor/oxide interface by a contactless charge technique 有权
标题翻译：通过非接触充电技术确定半导体/氧化物界面的阱密度的方法
公开(公告)号：US06391668B1
公开(公告)日：2002-05-21
申请号：US09562346
申请日：2000-05-01
申请人： Carlos M. Chacon , Sundar S. Chetlur , Brian E. Harding , Minesh A. Patel , Pradip K. Roy
发明人： Carlos M. Chacon , Sundar S. Chetlur , Brian E. Harding , Minesh A. Patel , Pradip K. Roy
IPC分类号： H01L2166
CPC分类号： H01L22/14
摘要： The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.
摘要翻译：本发明提供一种确定半导体衬底/电介质界面的阱密度的方法。在一个实施例中，该方法包括测量由位于接口附近的陷阱的载流子导致的半导体衬底内的电流，其中测量的电流是位于界面处的陷阱的数量的函数，并且将陷阱密度确定为测量电流的函数。

2. 发明授权

US06674151B1 Deuterium passivated semiconductor device having enhanced immunity to hot carrier effects 有权
标题翻译：氘钝化半导体器件具有增强的对热载流子效应的抗扰性
公开(公告)号：US06674151B1
公开(公告)日：2004-01-06
申请号：US09379055
申请日：1999-08-23
申请人： Sundar S. Chetlur , Pradip K. Roy , Anthony S. Oates , Sidhartha Sen , Jonathan Z-N. Zhou
发明人： Sundar S. Chetlur , Pradip K. Roy , Anthony S. Oates , Sidhartha Sen , Jonathan Z-N. Zhou
IPC分类号： H01L29167
CPC分类号： H01L21/28211 , H01L21/28176 , H01L21/3003 , H01L21/76843
摘要： A semiconductor device having trap sites passivated with deuterium has enhanced immunity to hot carrier effects. The trap sites which are passivated with deuterium are encapsulated beneath a barrier film and are therefore resistant to having the deuterium diffuse away from the trap sites during subsequent high temperature processing operations.
摘要翻译：具有用氘钝化的捕获位点的半导体器件增强了对热载体效应的免疫力。用氘钝化的捕集点被封装在阻挡膜下面，因此在随后的高温处理操作期间，氘能够使氘扩散离开捕获位点。

3. 发明授权

US06693434B2 Automated system for estimating ring oscillator reliability and testing AC response and method of operation thereof 失效
标题翻译：用于估计环形振荡器可靠性和测试交流响应的自动化系统及其操作方法
公开(公告)号：US06693434B2
公开(公告)日：2004-02-17
申请号：US09768729
申请日：2001-01-24
申请人： Sundar S. Chetlur , Pradip K. Roy , Johathan Z. Zhou
发明人： Sundar S. Chetlur , Pradip K. Roy , Johathan Z. Zhou
IPC分类号： G01R313163
CPC分类号： G01R31/27 , G01R31/2824
摘要： An automated system for, and method of estimating ring oscillator reliability and testing AC response of a device under test (DUT). In one embodiment, the system includes: (1) a DUT board that accepts, and allows electrical communication with, a plurality of DUTs, (2) a power source, couplable to the DUT board, that provides AC power of controllable characteristics to the plurality of DUTs and (3) an automated switching matrix, couplable between the DUT board and a circuit analyzer, that allows the circuit analyzer to analyze ring oscillators and predetermined portions of the plurality of DUTs at predetermined times as the power source provides the power thereto.
摘要翻译：一种用于估计环形振荡器可靠性和测试被测设备（DUT）的交流响应的自动化系统及方法。在一个实施例中，系统包括：（1）DUT板，其接受并允许与多个DUT进行电气通信，（2）可耦合到DUT板的电源，其向所述DUT板提供可控特性的AC功率多个DUT和（3）自动切换矩阵，可耦合在DUT板和电路分析器之间，允许电路分析仪在电源向其提供电力的情况下在预定时间内分析环形振荡器和多个DUT的预定部分。

4. 发明授权

US06187665B1 Process for deuterium passivation and hot carrier immunity 有权
标题翻译：氘钝化和热载体免疫的方法
公开(公告)号：US06187665B1
公开(公告)日：2001-02-13
申请号：US09378856
申请日：1999-08-23
申请人： Sundar S. Chetlur , Pradip K. Roy , Anthony S. Oates , Sidhartha Sen , Jonathan Z-N. Zhou
发明人： Sundar S. Chetlur , Pradip K. Roy , Anthony S. Oates , Sidhartha Sen , Jonathan Z-N. Zhou
IPC分类号： H01L21366
CPC分类号： H01L21/28211 , H01L21/28176 , H01L21/3003 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76843 , H01L21/76861
摘要： A process sequence for forming a semiconductor device utilizes a passivation annealing process using deuterium which enhances immunity to hot carrier effects and extends device lifetime. The process sequence is carried out prior to the introduction of metal conductive films to the device. The process sequence includes a three-step passivation, de-passivation, re-passivation sequence and utilizes a barrier film to encapsulate deuterium molecules in the vicinity of a gate oxide, during the de-passivation operation.
摘要翻译：用于形成半导体器件的工艺顺序利用使用氘的钝化退火工艺，其增强了对热载流子效应的抗扰性并延长了器件寿命。在将金属导电膜引入器件之前进行处理顺序。在去钝化操作期间，工艺顺序包括三步钝化，去钝化，再钝化序列，并且利用阻挡膜将氘分子包封在栅氧化物附近。

5. 发明授权

US06255128B1 Non-contact method for determining the presence of a contaminant in a semiconductor device 失效
标题翻译：用于确定半导体器件中污染物的存在的非接触方法
公开(公告)号：US06255128B1
公开(公告)日：2001-07-03
申请号：US09130240
申请日：1998-08-06
申请人： Carlos M. Chacon , Pradip K. Roy
发明人： Carlos M. Chacon , Pradip K. Roy
IPC分类号： B01R3126
CPC分类号： G01N27/002 , H01L22/12
摘要： The present invention provides a non-contact method for determining whether a contaminant is present in a semiconductor wafer having a substrate/dielectric interface formed thereon. in one advantageous embodiment, the method comprises field inducing a junction in equilibrium inversion in the semiconductor wafer device. A conventional corona source may be used to induce the junction to equilibrium inversion. This particular embodiment further includes forming a contaminant junction near the substrate/dielectric interface when the contaminant is present in the semiconductor wafer by adding charge and pulsing the junction out of equilibrium. A surface voltage measurement, which may be taken with a Kelvin probe, is obtained by measuring a change in a surface voltage as a function of time. The method further includes determining whether the contaminant is present in the semiconductor wafer from the change in the surface voltage. When the contaminant is present in the device, the change in the surface voltage is negligible. This negligible change is in stark contrast to the change in surface voltage that occurs in a non-contaminated device. The data obtained from these surface voltages can be plotted with conventional devices to yield the change in surface voltage with respect to time.
摘要翻译：本发明提供了一种用于确定在其上形成有衬底/电介质界面的半导体晶片中是否存在污染物的非接触方法。在一个有利的实施例中，该方法包括在半导体晶片装置中的场平衡反转中的场感应。传统的电晕源可以用来诱导结到平衡反转。该特定实施例还包括当通过添加电荷并将结合脉冲到平衡之外，当污染物存在于半导体晶片中时，在衬底/电介质界面附近形成污染物结。通过测量作为时间的函数的表面电压的变化可获得可以用开尔文探针进行的表面电压测量。该方法还包括根据表面电压的变化确定污染物是否存在于半导体晶片中。当设备中存在污染物时，表面电压的变化可以忽略不计。这个微不足道的变化与在非污染设备中发生的表面电压的变化形成鲜明的对比。从这些表面电压获得的数据可以用常规装置绘制，以产生相对于时间的表面电压的变化。

6. 发明授权

US06605529B2 Method of creating hydrogen isotope reservoirs in a semiconductor device 失效
公开(公告)号：US06605529B2
公开(公告)日：2003-08-12
申请号：US09853317
申请日：2001-05-11
申请人： Sundar Chetlur , Jennifer M. McKinley , Minesh A. Patel , Pradip K. Roy , Jonathan Zhong-Ning Zhou
发明人： Sundar Chetlur , Jennifer M. McKinley , Minesh A. Patel , Pradip K. Roy , Jonathan Zhong-Ning Zhou
IPC分类号： H01L214763
CPC分类号： H01L21/28194 , H01L21/28035 , H01L21/28176 , H01L21/28211 , H01L21/3003 , H01L29/4925 , H01L29/51 , H01L29/513
摘要： The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.

7. 发明授权

US06664800B2 Non-contact method for determining quality of semiconductor dielectrics 有权
标题翻译：用于确定半导体电介质质量的非接触方法
公开(公告)号：US06664800B2
公开(公告)日：2003-12-16
申请号：US09756965
申请日：2001-01-08
申请人： Carlos M. Chacon , Sundar Chetlur , Pradip K. Roy
发明人： Carlos M. Chacon , Sundar Chetlur , Pradip K. Roy
IPC分类号： G01R3100
CPC分类号： G01R31/2648 , G01R31/129
摘要： A non-contact method for determining a quality of a semiconductor dielectric. The method includes depositing a charge on a dielectric to achieve a high voltage on the dielectric, measuring a voltage drop of the dielectric as a function of time, and determining a soft breakdown voltage of the dielectric from the voltage drop as a function of time. The amount of charge that is deposited may vary. For example, the charge may be deposited until a voltage that ranges from about 4 megavolts to about 16 megavolts is achieved on the dielectric. The amount of charge may also depend on the thickness of the dielectric. For example, applying a charge as a function of the thickness may include applying 4 megavolts when the thickness is about 1.2 nm or applying 16 megavolts when the thickness is about 5.0 nm.
摘要翻译：一种用于确定半导体电介质质量的非接触方法。该方法包括在电介质上沉积电荷以在电介质上实现高电压，测量作为时间的函数的电介质的电压降，以及根据时间从电压降确定电介质的软击穿电压。存放的电荷量可能会有所不同。例如，可以在电介质上实现电荷，直到达到约4兆伏特至约16兆伏特的电压。电荷量也可以取决于电介质的厚度。例如，作为厚度的函数施加电荷可以包括当厚度为约1.2nm时应用4兆伏，或者当厚度为约5.0nm时施加16兆伏特。

8. 发明授权

US06548422B1 Method and structure for oxide/silicon nitride interface substructure improvements 有权
标题翻译：改善氧化物/氮化硅界面亚结构的方法和结构
公开(公告)号：US06548422B1
公开(公告)日：2003-04-15
申请号：US09966779
申请日：2001-09-27
申请人： Pradip K. Roy , David C. Brady , Carlos M. Chacon
发明人： Pradip K. Roy , David C. Brady , Carlos M. Chacon
IPC分类号： H01L2348
CPC分类号： H01L21/28185 , H01L21/02332 , H01L21/0234 , H01L21/28202 , H01L21/28211 , H01L29/513 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A transistor gate dielectric structure includes an oxide layer formed on a substrate, a superjacent nitride layer and a transition layer interposed therebetween. The presence of the transition layer alleviates stress between the nitride and oxide layers and minimizes any charge trapping sites between the nitride and oxide layers. The transition layer includes both nitrogen and oxygen as components. The method for forming the structure includes forming the transition layer using a remote nitridation reactor at a sufficiently low temperature such that virtually no nitrogen reaches the interface formed between the oxide layer and the substrate. The oxide layer/substrate interface is relatively pristine and defect-free. In an exemplary embodiment, the oxide layer may be a graded structure formed using two distinct processing operations, a first operation at a relatively low temperature and a final operation at a temperature above the viscoelastic temperature of the oxide film.
摘要翻译：晶体管栅极电介质结构包括形成在衬底上的氧化物层，超临界氮化物层和介于其间的过渡层。过渡层的存在减轻氮化物和氧化物层之间的应力，并使氮化物和氧化物层之间的任何电荷俘获位置最小化。过渡层包括氮和氧作为组分。形成结构的方法包括在足够低的温度下使用远程氮化反应器形成过渡层，使得实际上没有氮到达氧化物层和衬底之间形成的界面。氧化物层/衬底界面相对原始且无缺陷。在示例性实施例中，氧化物层可以是使用两种不同的加工操作形成的渐变结构，在较低温度下的第一操作和在高于氧化膜的粘弹性温度的温度下的最终操作。

9. 发明授权

US06265890B1 In-line non-contact depletion capacitance measurement method and apparatus 失效
标题翻译：在线非接触耗尽电容测量方法和装置
公开(公告)号：US06265890B1
公开(公告)日：2001-07-24
申请号：US09383457
申请日：1999-08-26
申请人： Carlos M. Chacon , Sailesh Chittipeddi , Pradip K. Roy
发明人： Carlos M. Chacon , Sailesh Chittipeddi , Pradip K. Roy
IPC分类号： G01R3102
CPC分类号： G01R27/2611
摘要： A method and apparatus for in-line, non-contact depletion capacitance measurement of a semiconductor wafer using non-contact voltage measurement and non-contact surface photovoltage response.
摘要翻译：一种使用非接触电压测量和非接触表面光电压响应的半导体晶片的在线非接触耗尽电容测量的方法和装置。

10. 发明授权

US06207468B1 Non-contact method for monitoring and controlling plasma charging damage in a semiconductor device 失效
标题翻译：用于监测和控制半导体器件中的等离子体充电损伤的非接触方法
公开(公告)号：US06207468B1
公开(公告)日：2001-03-27
申请号：US09178317
申请日：1998-10-23
申请人： Carlos M. Chacon , Pradip K. Roy
发明人： Carlos M. Chacon , Pradip K. Roy
IPC分类号： H01L2166
CPC分类号： H01L22/12
摘要： The present invention provides a method for controlling a process parameter for fabricating a semiconductor wafer. In one embodiment, the method includes forming a test substrate using a given process parameter, determining a flatband voltage of the test substrate, and modifying the given process parameter to cause the flatband voltage to approach zero. The process parameter that is modified to cause the flatband voltage to approach zero may vary. The flatband may be determined by a non-contact method, which uses a kelvin probe to measure the flatband voltage and a corona source to deposit a charge on the test substrate.
摘要翻译：本发明提供一种用于控制用于制造半导体晶片的工艺参数的方法。在一个实施例中，该方法包括使用给定的工艺参数形成测试衬底，确定测试衬底的平带电压，以及修改给定的工艺参数以使扁平带电压接近零。修改以使扁平电压接近零的工艺参数可能会有所不同。扁平带可以通过使用开尔文探针来测量平带电压的非接触方法来确定，并且电晕源可以在测试基板上沉积电荷。

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