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1. 发明授权

US07319623B1 Method for isolating a failure site in a wordline in a memory array 有权
标题翻译：隔离存储器阵列中的字线中的故障位置的方法
公开(公告)号：US07319623B1
公开(公告)日：2008-01-15
申请号：US10981026
申请日：2004-11-04
申请人： Caiwen Yuan , Susan Xia Li , Andy Gray
发明人： Caiwen Yuan , Susan Xia Li , Andy Gray
IPC分类号： G11C7/00
CPC分类号： H01L27/1052
摘要： According to one exemplary embodiment, a method for isolating a failure site in a leaky wordline in a memory array includes dividing said leaky wordline into an initial leaky wordline portion and an initial non-leaky wordline portion, where the initial leaky wordline portion has wordline-to-substrate leakage. The initial leaky wordline portion can be determined by using a passive voltage contrast procedure to illuminate the initial leaky wordline portion. The method further includes performing a number of division and identification cycles on the initial leaky wordline portion to determine a final leaky wordline portion. According to this exemplary embodiment, the final leaky wordline portion comprises a predetermined number of memory cells. The method further includes performing a cutting and imaging procedure on the final leaky wordline portion to isolate the failure site.
摘要翻译：根据一个示例性实施例，一种用于隔离存储器阵列中的泄漏字线中的故障位置的方法包括将所述泄漏字线划分为初始泄漏字线部分和初始非泄露字线部分，其中初始泄漏字线部分具有字线 - 到基板泄漏。初始泄漏字线部分可以通过使用被动电压对比程序来确定来照亮初始泄漏字线部分。该方法还包括在初始泄漏字线部分上执行多个分割和识别周期以确定最终的泄漏字线部分。根据该示例性实施例，最终的泄漏字线部分包括预定数量的存储单元。该方法还包括对最终的泄漏字线部分执行切割和成像过程以隔离故障部位。

2. 发明授权

US06991946B1 Method and system for providing backside voltage contrast for silicon on insulator devices 失效
标题翻译：为绝缘体上硅器件提供背面电压对比度的方法和系统
公开(公告)号：US06991946B1
公开(公告)日：2006-01-31
申请号：US10701877
申请日：2003-11-05
申请人： Mehrdad Mahanpour , Mohammad Massodi , Caiwen Yuan
发明人： Mehrdad Mahanpour , Mohammad Massodi , Caiwen Yuan
IPC分类号： H01L21/66
CPC分类号： G01R31/2898 , G01R31/307
摘要： The present inventive principles provide a method and system for performing backside voltage contrast on an SOI device. The SOI semiconductor device includes a bulk silicon, a box insulator residing on the bulk silicon and a silicon region on the box insulator. The SOI semiconductor device further includes a plurality of structures in the silicon region, the plurality of structures includes a conductive structure. The method and system include mechanical dimpling and chemical etching of the substrate to expose the box insulator. Optionally, a second chemical etch to remove at least a portion of the box insulator may be performed. A charged particle beam, such as energetic electrons from an SEM, for example, may be directed at the backside of the device, and emitted secondary electrons observed.
摘要翻译：本发明的原理提供了一种用于在SOI器件上执行背面电压对比度的方法和系统。 SOI半导体器件包括体硅，位于体硅上的盒绝缘体和盒绝缘体上的硅区。 SOI半导体器件还包括硅区域中的多个结构，所述多个结构包括导电结构。该方法和系统包括基板的机械凹坑和化学蚀刻以暴露盒式绝缘体。可选地，可以执行用于去除盒绝缘体的至少一部分的第二化学蚀刻。例如，诸如来自SEM的高能电子的带电粒子束可以指向器件的背面，并且观察到发射的二次电子。

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