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1. 发明授权

US11201557B2 Control system for synchronous rectifying transistor of LLC converter 有权
公开(公告)号：US11201557B2
公开(公告)日：2021-12-14
申请号：US16959116
申请日：2018-12-29
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD. , SOUTHEAST UNIVERSITY
发明人： Qinsong Qian , Shengyou Xu , Feng Lin , Hao Wang , Wei Su , Qi Liu , Longxing Shi
IPC分类号： H02M3/335 , H02M1/00 , H02M3/00
摘要： A control system for synchronous rectifying transistor of LLC converter, the system comprising a voltage sampling circuit, a high-pass filtering circuit, a PI compensation and effective value detection circuit, and a control system taking a microcontroller (MCU) as a core. When the LLC converter is operating at a high frequency, a drain-source voltage VDS(SR) of the synchronous rectifying transistor delivers, via the sampling circuit, a change signal of the drain-source voltage during turn-off into the high-pass filtering circuit and the PI compensation and effective value detection circuit to obtain an effective value amplification signal of a drain-source voltage oscillation signal caused by parasitic parameters, and the current value is compared with a previously collected value via a control circuit taking a microcontroller (MCU) as a core, so as to change a turning-on time of the synchronous rectifying transistor in the next period.

2. 发明授权

US10340906B2 Integrated bootstrap high-voltage driver chip and technological structure thereof 有权
公开(公告)号：US10340906B2
公开(公告)日：2019-07-02
申请号：US15779432
申请日：2017-01-23
申请人： SOUTHEAST UNIVERSITY , SOUTHEAST UNIVERSITY-WUXI INTEGRATED CIRCUIT TECHNOLOGY RESEARCH INSTITUTE
发明人： Weifeng Sun , Yunwu Zhang , Kuo Yu , Jing Zhu , Shen Xu , Qinsong Qian , Siyang Liu , Shengli Lu , Longxing Shi
IPC分类号： H02M3/07 , H03K17/06 , H03K17/16 , H03K17/687 , H03K19/0185 , H01L27/07 , H01L29/78 , H01L29/423 , H01L29/10
摘要： Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.

3. 发明授权

US11081967B2 Self-adaptive synchronous rectification control system and method of active clamp flyback converter 有权
公开(公告)号：US11081967B2
公开(公告)日：2021-08-03
申请号：US16617508
申请日：2018-09-28
申请人： SOUTHEAST UNIVERSITY
发明人： Qinsong Qian , Shengyou Xu , Qi Liu , Weifeng Sun , Shengli Lu , Longxing Shi
IPC分类号： H02M3/335 , H02M1/08 , H02M1/00
摘要： The invention discloses a self-adaptive synchronous rectification control system and a self-adaptive synchronous rectification control method of an active clamp flyback converter. The control system comprises a sampling and signal processing circuit, a control circuit with a microcontroller as a core and a gate driver. According to the control method, a switching-on state, an early switching-off state, a late switching-off state and an exact switching-off state of a secondary synchronous rectifier of the active clamp flyback converter can be directly detected, and the synchronous rectifier and a switching-on time of the synchronous rectifier in next cycle can be controlled according to a detection result. After several cycles of self-adaptive control, the synchronous rectifier enters the exact switching-on state, thus avoiding oscillation of an output waveform of the active clamp flyback converter.

4. 发明授权

US09159818B2 High-current N-type silicon-on-insulator lateral insulated-gate bipolar transistor 有权
标题翻译：大电流N型绝缘体上半导体绝缘栅双极晶体管
公开(公告)号：US09159818B2
公开(公告)日：2015-10-13
申请号：US14349632
申请日：2012-10-24
申请人： SOUTHEAST UNIVERSITY
发明人： Weifeng Sun , Siyang Liu , Jing Zhu , Qinsong Qian , Shen Xu , Shengli Lu , Longxing Shi
IPC分类号： H01L27/24 , H01L29/739 , H01L29/40 , H01L27/12 , H01L29/06 , H01L27/06
CPC分类号： H01L29/7394 , H01L27/0623 , H01L27/1203 , H01L29/0638 , H01L29/404
摘要： A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.
摘要翻译：一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

5. 发明申请

US20140203406A1 ISOLATION STRUCTURE OF HIGH-VOLTAGE DRIVING CIRCUIT 有权
标题翻译：高压驱动电路隔离结构
公开(公告)号：US20140203406A1
公开(公告)日：2014-07-24
申请号：US14240287
申请日：2012-08-14
申请人： SOUTHEAST UNIVERSITY
发明人： Longxing Shi , Qinsong Qian , Weifeng Sun , Jing Zhu , Xianguo Huang , Shengli Lu
IPC分类号： H01L29/06 , H01L21/8234 , H01L21/761
CPC分类号： H01L29/0646 , H01L21/265 , H01L21/761 , H01L21/823481 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/7835
摘要： An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.
摘要翻译：高电压驱动电路的隔离结构包括P型衬底和P型外延层; 在P型外延层上布置有高电压区域，低电压区域和高低压端子区域; 在高低压区和低电压区之间设置第一P型结隔离区，高电压区与低压区之间设置高压绝缘栅场效应管; 高压绝缘栅场效应管的两侧和高压绝缘栅场效应管与高边区之间的隔离结构形成为第二P型结隔离区。

6. 发明授权

US09240469B2 Transverse ultra-thin insulated gate bipolar transistor having high current density 有权
标题翻译：具有高电流密度的横向超薄绝缘栅双极晶体管
公开(公告)号：US09240469B2
公开(公告)日：2016-01-19
申请号：US14439715
申请日：2012-12-27
申请人： SOUTHEAST UNIVERSITY
发明人： Weifeng Sun , Jing Zhu , Shen Xu , Qinsong Qian , Siyang Liu , Shengli Lu , Longxing Shi
IPC分类号： H01L29/66 , H01L29/739 , H01L29/06 , H01L29/49 , H01L29/10 , H01L29/08 , H01L23/528
CPC分类号： H01L29/7394 , H01L23/528 , H01L29/0611 , H01L29/0696 , H01L29/0808 , H01L29/0821 , H01L29/0847 , H01L29/1008 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.
摘要翻译：具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

7. 发明授权

US12132407B1 Adaptive load optimization method for resonant gate drive circuit 有权
公开(公告)号：US12132407B1
公开(公告)日：2024-10-29
申请号：US18735204
申请日：2024-06-06
申请人： SOUTHEAST UNIVERSITY
发明人： Qinsong Qian , Ziyan Zhou , Yufan Wang , Qiang Luo , Weifeng Sun , Longxing Shi
IPC分类号： H02M3/335 , H02M1/00 , H02M1/088 , H02M3/00
CPC分类号： H02M3/33573 , H02M1/0009 , H02M1/0054 , H02M1/088 , H02M3/01 , H02M3/33576
摘要： An adaptive load optimization method for a resonant gate drive circuit is provided to optimize the switching loss, turn-on loss and gate drive loss under different MOSFET loads. A data table is pre-stored in a digital signal processor chip (DSP), and voltages and pre-charge times, corresponding to a low total loss, of the resonant gate driver obtained by actual tests in case of different load currents are recorded in the data table; and in actual application, after an analog-to-digital converter terminal (ADC) samples a load current, a load current, closest to the sampled load current, is read from the data table, and the digital signal processor chip (DSP) is enabled to perform table look-up to obtain an optimized voltage and pre-charge time of a gate drive circuit.

8. 发明申请

US20150270377A1 TRANSVERSE ULTRA-THIN INSULATED GATE BIPOLAR TRANSISTOR HAVING HIGH CURRENT DENSITY 有权
标题翻译：具有高电流密度的横向超薄绝缘栅双极晶体管
公开(公告)号：US20150270377A1
公开(公告)日：2015-09-24
申请号：US14439715
申请日：2012-12-27
申请人： SOUTHEAST UNIVERSITY
发明人： Weifeng Sun , Jing Zhu , Shen Xu , Qinsong Qian , Siyang Liu , Shengli Lu , Longxing Shi
IPC分类号： H01L29/739 , H01L23/528 , H01L29/10 , H01L29/08 , H01L29/06 , H01L29/49
CPC分类号： H01L29/7394 , H01L23/528 , H01L29/0611 , H01L29/0696 , H01L29/0808 , H01L29/0821 , H01L29/0847 , H01L29/1008 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.
摘要翻译：具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

9. 发明授权

US12062985B1 Control method for four-switch buck-boost converter 有权
公开(公告)号：US12062985B1
公开(公告)日：2024-08-13
申请号：US18566102
申请日：2022-09-26
申请人： SOUTHEAST UNIVERSITY
发明人： Qi Liu , Weiwei Zhai , Leilei Shi , Qinsong Qian , Weifeng Sun , Longxing Shi
IPC分类号： H02M3/158 , H02M1/00 , H02M1/088
CPC分类号： H02M3/1582 , H02M1/0058 , H02M1/088
摘要： A control method for a four-switch buck-boost converter is provided. The control method adopts four-stage control, and divides the load range into two sections and adopts different control strategies according to a critical load value corresponding to optimal control. In Boost mode, before the critical load, T1 and T2 are kept constant, T3 is a minimum value for realizing soft-switching, and T4 decreases with the increase of the load; when the critical load is reached, T4 drops to 0; and after the critical load, T1, T2, T3 and T increase with the load. In Buck mode, before the critical load, T2 and T3 are kept constant, T1 is a minimum value for realizing soft-switching, and T4 decreases with the increase of the load; when the critical load is reached, T4 drops to 0; and after the critical load, T1, T2, T3 and T increase with the load.

10. 发明申请

US20140306266A1 HIGH-CURRENT N-TYPE SILICON-ON-INSULATOR LATERAL INSULATED-GATE BIPOLAR TRANSISTOR 有权
标题翻译：高电流N型绝缘子硅酸盐绝缘栅双极晶体管
公开(公告)号：US20140306266A1
公开(公告)日：2014-10-16
申请号：US14349632
申请日：2012-10-24
申请人： SOUTHEAST UNIVERSITY
发明人： Weifeng Sun , Siyang Liu , Jing Zhu , Qinsong Qian , Shen Xu , Shengli Lu , Longxing Shi
IPC分类号： H01L29/739 , H01L27/12 , H01L27/06
CPC分类号： H01L29/7394 , H01L27/0623 , H01L27/1203 , H01L29/0638 , H01L29/404
摘要： A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.
摘要翻译：一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

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