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1. 发明授权

US10340906B2 Integrated bootstrap high-voltage driver chip and technological structure thereof 有权
公开(公告)号：US10340906B2
公开(公告)日：2019-07-02
申请号：US15779432
申请日：2017-01-23
申请人： SOUTHEAST UNIVERSITY , SOUTHEAST UNIVERSITY-WUXI INTEGRATED CIRCUIT TECHNOLOGY RESEARCH INSTITUTE
发明人： Weifeng Sun , Yunwu Zhang , Kuo Yu , Jing Zhu , Shen Xu , Qinsong Qian , Siyang Liu , Shengli Lu , Longxing Shi
IPC分类号： H02M3/07 , H03K17/06 , H03K17/16 , H03K17/687 , H03K19/0185 , H01L27/07 , H01L29/78 , H01L29/423 , H01L29/10
摘要： Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.

2. 发明授权

US09159818B2 High-current N-type silicon-on-insulator lateral insulated-gate bipolar transistor 有权
标题翻译：大电流N型绝缘体上半导体绝缘栅双极晶体管
公开(公告)号：US09159818B2
公开(公告)日：2015-10-13
申请号：US14349632
申请日：2012-10-24
申请人： SOUTHEAST UNIVERSITY
发明人： Weifeng Sun , Siyang Liu , Jing Zhu , Qinsong Qian , Shen Xu , Shengli Lu , Longxing Shi
IPC分类号： H01L27/24 , H01L29/739 , H01L29/40 , H01L27/12 , H01L29/06 , H01L27/06
CPC分类号： H01L29/7394 , H01L27/0623 , H01L27/1203 , H01L29/0638 , H01L29/404
摘要： A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.
摘要翻译：一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

3. 发明授权

US11777416B2 Flyback converter and output voltage acquisition method therefor and apparatus thereof 有权
公开(公告)号：US11777416B2
公开(公告)日：2023-10-03
申请号：US17418606
申请日：2019-12-19
申请人： SOUTHEAST UNIVERSITY , CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Weifeng Sun , Huaxin Zhang , Hu Zhang , Menglin Yu , Siyu Zhao , Shen Xu , Longxing Shi
IPC分类号： H02M3/335
CPC分类号： H02M3/33592
摘要： A flyback converter and an output voltage acquisition method therefor and apparatus thereof, wherein the output voltage acquisition method comprises the following steps: acquiring the reference output voltage of a flyback converter; sampling the current output voltage of the flyback converter within a reset time of each switching period among M continuous switching periods of the flyback converter, wherein M is a positive integer; and according to the reference output voltage and the current output voltage, sampling a dichotomy to successively approximate the current output voltage until the M switching periods are finished, and acquiring the output voltage of the flyback converter.

4. 发明授权

US11557959B2 Deadtime automatic-optimization system for flyback power supply having primary-side feedback in CCM, control system and method for flyback power supply having primary-side feedback in CCM 有权
公开(公告)号：US11557959B2
公开(公告)日：2023-01-17
申请号：US16959015
申请日：2018-12-29
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD. , SOUTHEAST UNIVERSITY
发明人： Shen Xu , Minggang Chen , Hao Wang , Jinyu Xiao , Wei Su , Weifeng Sun , Longxing Shi
IPC分类号： H02M1/38 , H02M1/08 , H02M3/335 , H02M1/00
摘要： An automatic dead zone time optimization system in a primary-side regulation flyback power supply continuous conduction mode (CCM), including a closed loop formed by a control system, including a single output digital to analog converter (DAC) midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a pulse-width modulation (PWM) driving module, and a controlled synchronous rectification primary-side regulation flyback converter. A primary-side current is sampled using a DAC Sampling mechanism to calculate a secondary-side average current, so as to obtain a primary-side average current and a secondary-side average current, in the case of CCM. A secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time; and the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time.

5. 发明申请

US20140306266A1 HIGH-CURRENT N-TYPE SILICON-ON-INSULATOR LATERAL INSULATED-GATE BIPOLAR TRANSISTOR 有权
标题翻译：高电流N型绝缘子硅酸盐绝缘栅双极晶体管
公开(公告)号：US20140306266A1
公开(公告)日：2014-10-16
申请号：US14349632
申请日：2012-10-24
申请人： SOUTHEAST UNIVERSITY
发明人： Weifeng Sun , Siyang Liu , Jing Zhu , Qinsong Qian , Shen Xu , Shengli Lu , Longxing Shi
IPC分类号： H01L29/739 , H01L27/12 , H01L27/06
CPC分类号： H01L29/7394 , H01L27/0623 , H01L27/1203 , H01L29/0638 , H01L29/404
摘要： A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.
摘要翻译：一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

6. 发明授权

US11984813B2 Synchronous rectification control system and method for quasi-resonant flyback converter 有权
公开(公告)号：US11984813B2
公开(公告)日：2024-05-14
申请号：US17435789
申请日：2020-05-15
申请人： SOUTHEAST UNIVERSITY , CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Shen Xu , Siyu Zhao , Congming Qi , Sen Zhang , Xiaoyu Shi , Weifeng Sun , Longxing Shi
IPC分类号： H02M3/335 , H02M1/00 , H02M1/38
CPC分类号： H02M3/33592 , H02M1/0058 , H02M1/38
摘要： A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.

7. 发明申请

US20150270377A1 TRANSVERSE ULTRA-THIN INSULATED GATE BIPOLAR TRANSISTOR HAVING HIGH CURRENT DENSITY 有权
标题翻译：具有高电流密度的横向超薄绝缘栅双极晶体管
公开(公告)号：US20150270377A1
公开(公告)日：2015-09-24
申请号：US14439715
申请日：2012-12-27
申请人： SOUTHEAST UNIVERSITY
发明人： Weifeng Sun , Jing Zhu , Shen Xu , Qinsong Qian , Siyang Liu , Shengli Lu , Longxing Shi
IPC分类号： H01L29/739 , H01L23/528 , H01L29/10 , H01L29/08 , H01L29/06 , H01L29/49
CPC分类号： H01L29/7394 , H01L23/528 , H01L29/0611 , H01L29/0696 , H01L29/0808 , H01L29/0821 , H01L29/0847 , H01L29/1008 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.
摘要翻译：具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

8. 发明授权

US12046990B1 Multi-phase high-precision current sharing control method applied to constant on-time control 有权
公开(公告)号：US12046990B1
公开(公告)日：2024-07-23
申请号：US18641384
申请日：2024-04-21
申请人： SOUTHEAST UNIVERSITY
发明人： Shen Xu , Haiqing Zhang , Yujie Liu , Ruizhi Wang , Yuan Gao , Yongjia Li , Weifeng Sun , Longxing Shi
IPC分类号： H02M1/08 , H02M1/00 , H02M3/158
CPC分类号： H02M1/082 , H02M1/0025 , H02M3/1586
摘要： A multi-phase high-precision current sharing control method applied to constant on-time control is provided, wherein a current difference between continuously sampled current of each line and mean current is processed by a PI compensation module and a low-pass filter module to obtain on-time regulation data. A high bit of the regulation data controls the value of counter reference Vref in an on-time control module, and a low bit controls the length of an enabled delay line in a delay line module. The counter timing control of the on-time control module is combined with the delay line timing control of the delay line module to improve the control precision of a DPWM. The method takes COT control of a Buck converter as a typical application. Compared with a multi-phase COT controller without a current-sharing mechanism, the method can improve the stability and reliability of the system.

9. 发明授权

US11770076B2 System and method for controlling active clamp flyback converter 有权
公开(公告)号：US11770076B2
公开(公告)日：2023-09-26
申请号：US17420866
申请日：2020-06-19
申请人： SOUTHEAST UNIVERSITY , CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Shen Xu , Minggang Chen , Wanqing Yang , Dejin Wang , Rui Jiang , Weifeng Sun , Longxing Shi
IPC分类号： H02M3/335 , H02M1/38 , H02M1/34
CPC分类号： H02M3/33569 , H02M1/342 , H02M1/38 , H02M3/33523
摘要： Disclosed are a system and method for controlling an active clamp flyback (ACF) converter. The system includes: a drive module configured to control turning-on or turning-off of a main switching transistor SL and a clamp switching transistor SH; a main switching transistor voltage sampling circuit configured to sample a voltage drop between an input terminal and an output terminal of the main switching transistor SL; a first comparator connected to the main switching transistor voltage sampling circuit and configured to determine whether a sampled first sampling voltage is a positive voltage or a negative voltage; and a dead time calculation module configured to adjust, according to an output of the first comparator and a main switching transistor control signal DUTYL of a current cycle, a clamp switching transistor control signal DUTYH of next cycle outputted by the drive module.

10. 发明授权

US11323039B2 Method for improving conversion efficiency of CCM mode of flyback resonant switch power supply 有权
公开(公告)号：US11323039B2
公开(公告)日：2022-05-03
申请号：US16959001
申请日：2018-12-29
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD. , SOUTHEAST UNIVERSITY
发明人： Weifeng Sun , Rongrong Tao , Hao Wang , Jinyu Xiao , Wei Su , Shen Xu , Longxing Shi
IPC分类号： H02M3/335 , H03K5/24 , H02M1/00
摘要： A method for improving the conversion efficiency of a CCM mode of a flyback resonant switch power supply, comprising: presetting a critical value Tset, calculating a time interval Ttap between adjacent zero points in the current connection time, outputting a shutdown signal at the zero points, and comparing the time interval Ttap with the preset critical value Tset; when Ttap>Tset, controlling the current shutdown time to be less than the shutdown time of the preceding cycle and outputting a start signal; when Ttap=0, controlling the current shutdown time to be greater than the shutdown time of the preceding cycle and outputting a start signal; and when 0

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