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1. 发明公开

EP0206929A1 Procédé de fabrication d'un circuit intégré et notamment d'une mémoire eprom comportant deux composants distincts isolés électriquement. 有权
标题翻译：具有两个不同，电绝缘部件制造集成电路，特别是EPROM存储器的方法。
公开(公告)号：EP0206929A1
公开(公告)日：1986-12-30
申请号：EP86401321
申请日：1986-06-17
申请人： COMMISSARIAT ENERGIE ATOMIQUE
发明人： HARTMANN JOEL , MARTIN FRANCOIS
IPC分类号： H01L27/112 , H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/82 , H01L29/60
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/11536
摘要： 1. Process for the production, on a semiconductor substrate (8), of an integrated circuit having at least two separate electrically insulated components, a first component (2) having a first insulant (10) surmounted by first (12) and second (14) stacked gates, which are separated by a second insulant (16), and a second component (22) having a third insulant (30) surmounted by a third gate (28), the first (10), second (16) and third (30) insulants having different, clearly defined thicknesses, characterized in that it comprises the following stages : a) producing a first insulant layer (110) on the substrate (8), b) covering the first insulant layer (110) with a first conductive layer (112), in which the first gate (12) will be formed, c) formation of a second insulant layer (112) on the first conductive layer (116), d) carrying out a first etching of the second insulant layer (116) and the first conductive layer (112) so as to only retain said second insulant and said conductive material in the region in which the first component will be produced, e) elimination of the first insulant layer (110) region located at the point where the second component will be produced, f) producing a third insulant layer (130) in said location, g) covering the structure obtained with a second conductive layer (114), h) producing the second (14) and third (28) gates by etching the second conductive layer (114) and i) producing the first gate (12) with the aid of a second etching of the second insulant layer (116) and the first conductive layer (112).
摘要翻译： 1.工艺进行生产，在具有至少两个分开的电绝缘部件，第一部件（2）具有由第一（12）顶上的第一绝缘材料（10）和第二集成电路的半导体衬底（8）（ 14）层叠栅，其通过由第三栅极（28顶上的第二绝缘材料（16），和一个第二部件（22）具有第三隔热材料（30）），所述第一（10分离），第二（16）和第三（30）insulants具有不同的，明确定义的厚度，dadurch gekennzeichnet，DASS它包括以下阶段：a）制备（8），b）盖着与所述第一绝缘材料层（110）在所述衬底上的第一绝缘材料层（110）第一导电层（112），其中所述第一栅极（12）将形成，c）将第一导电层（116）上的第二绝缘材料层（112）的形成，d）进行所述第二绝缘材料的第一蚀刻层（116）和所述第一导电层（112），以便只保留所述第二绝缘材料和所述导电材料钓鱼人，（在其中，所述第一组件将被产生，E的区域）位于其中，所述第二组件将被产生的点消除所述第一绝缘材料层（110）的区域中，f）产生第三绝缘材料层130）的所述位置，G）覆盖产生所述第二（14）和第三（28）门通过蚀刻所述第二导电层（114与第二导电层（114）获得的结构中，h））和i）的制造第一栅极（12）与所述第二绝缘材料层（116）和所述第一导电层（112）的第二蚀刻的帮助。

2. 发明专利

FR2957458A1 PROCEDE DE REALISATION D’UNE ELECTRODE CONDUCTRICE 未知
公开(公告)号：FR2957458A1
公开(公告)日：2011-09-16
申请号：FR1051832
申请日：2010-03-15
申请人： COMMISSARIAT ENERGIE ATOMIQUE
发明人： GASSILLOUD REMY , MARTIN FRANCOIS
IPC分类号： H01L21/44 , H01L21/328 , H01L21/70
摘要： La présente invention concerne un procédé de réalisation d'une électrode conductrice sur un substrat comportant les étapes suivantes : - dépôt d'une couche (213) réalisée dans un matériau diélectrique ; - dépôt sur la couche diélectrique d'une couche de protection (214) réalisée en nitrure d'un métal M ; - dépôt d'une couche de fonctionnalisation (215) réalisée dans un matériau comportant une espèce chimique E telle que l'enthalpie libre de formation du nitrure de cette espèce soit inférieure, en valeur absolue, à l'enthalpie libre de formation du nitrure de métal M de ladite couche de protection (214) sur une gamme de température comprise entre 0 et 1200°C ; - recuit (218) de l'ensemble comportant ladite couche de protection (214) et ladite couche de fonctionnalisation (215) de sorte que les espèces E diffusent de la couche de fonctionnalisation (215) vers la couche de protection (214) et les atomes d'azote migrent de la couche de protection (214) vers la couche de fonctionnalisation (215).

3. 发明专利

DE69811658T2 未知
公开(公告)号：DE69811658T2
公开(公告)日：2003-11-20
申请号：DE69811658
申请日：1998-05-04
申请人： COMMISSARIAT ENERGIE ATOMIQUE
发明人： GAUTIER JACQUES , MARTIN FRANCOIS
IPC分类号： H01L21/8247 , H01L27/10 , H01L29/06 , H01L29/76 , H01L29/78 , H01L29/788 , H01L29/792
摘要： A quantic effect device which functions using a Coulomb blockade phenomenon. The device includes two electron reservoirs, two sets of islands that are separated by a dielectric layer, a protective insulating layer and a control electrode.

4. 发明专利

DE69904069D1 未知
公开(公告)号：DE69904069D1
公开(公告)日：2003-01-02
申请号：DE69904069
申请日：1999-09-20
申请人： FRANCE TELECOM , COMMISSARIAT ENERGIE ATOMIQUE
发明人： MARTIN FRANCOIS , BENSAHEL DANIEL , HERNANDEZ CAROLINE , VALLIER LAURENT
IPC分类号： C23C8/28 , C23C28/04
摘要： Method for preparing a silicon substrate to form a thin electric insulating layer (24), characterized in that it comprises:a deoxidation step of at least one part of the silicon substrate (10), thena heat treatment step of the substrate at a temperature of 750° C. or less, the heat treatment being conducted in a NO-containing atmosphere at a pressure of 5.103 Pa (50 mBr) or less, in order to form a layer of silicon oxynitride (22) on the substrate. Use for the production of EPROM and DRAM memories.

5. 发明专利

FR2815026A1 未知
公开(公告)号：FR2815026A1
公开(公告)日：2002-04-12
申请号：FR0012797
申请日：2000-10-06
申请人： COMMISSARIAT ENERGIE ATOMIQUE
发明人： SEMERIA MARIE NOELLE , MUR PIERRE , FOURNEL FRANCK , MORICEAU HUBERT , EYMERY JOEL , MAGNEA NOEL , BARON THIERRY , MARTIN FRANCOIS
IPC分类号： C23C14/02 , C23C16/02 , C30B25/02 , B82B1/00 , B82B3/00
摘要： The invention concerns a device consisting of microstructures or nanostructures on a support. The invention is characterised in that the support comprises: a substrate (1) including at least a part made of crystalline material, said part having a surface (2) exhibiting a stress field or a topology associated with a stress field, the stress field being associated with dislocations; an intermediate layer (3) integral with said surface (2) and having a thickness and/or a composition and/or a state enabling transmission of said stress field through said layer up to its free surface which bears the microstructures or nanostructures (4).

6. 发明专利

FR2783530B1 未知
公开(公告)号：FR2783530B1
公开(公告)日：2001-08-31
申请号：FR9811746
申请日：1998-09-21
申请人： COMMISSARIAT ENERGIE ATOMIQUE
发明人： MARTIN FRANCOIS , BENSAHEL DANIEL , HERNANDEZ CAROLINE , VALLIER LAURENT
IPC分类号： C23C8/28 , C23C28/04 , C23C16/04 , H01L21/318
摘要： Method for preparing a silicon substrate to form a thin electric insulating layer (24), characterized in that it comprises:a deoxidation step of at least one part of the silicon substrate (10), thena heat treatment step of the substrate at a temperature of 750° C. or less, the heat treatment being conducted in a NO-containing atmosphere at a pressure of 5.103 Pa (50 mBr) or less, in order to form a layer of silicon oxynitride (22) on the substrate. Use for the production of EPROM and DRAM memories.

7. 发明专利

FR2757312A1 未知
公开(公告)号：FR2757312A1
公开(公告)日：1998-06-19
申请号：FR9615436
申请日：1996-12-16
申请人： COMMISSARIAT ENERGIE ATOMIQUE
发明人： DELEONIBUS SIMON , MARTIN FRANCOIS
IPC分类号： H01L29/43 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/423 , H01L29/49 , H01L29/78
摘要： The invention concerns a MIS transistor with self-aligned metal grid and the method for making it. The method consists in the following steps: a) producing on a substrate (100) a dummy grid in a material capable of resisting to a thermal treatment; b) forming in the substrate self-aligned source and drain regions (118, 120) on the dummy grid; c) laterally coating the dummy grid with an electrically insulating material (124, 126); d) eliminating the dummy grid and forming in its place a permanent grid (136) in a material with weak resistivity. The invention is useful for making ultrahigh frequency circuits.

8. 发明专利

DE69934362T2 未知
公开(公告)号：DE69934362T2
公开(公告)日：2008-01-10
申请号：DE69934362
申请日：1999-02-15
申请人： COMMISSARIAT ENERGIE ATOMIQUE
发明人： BENSAHEL DANIEL , CAMPIDELLI YVES , MARTIN FRANCOIS , HERNANDEZ CAROLINE
IPC分类号： H01L21/28 , H01L29/78 , H01L21/318 , H01L29/51

9. 发明专利

FR2809973B1 未知
公开(公告)号：FR2809973B1
公开(公告)日：2003-09-05
申请号：FR0007276
申请日：2000-06-07
申请人： COMMISSARIAT ENERGIE ATOMIQUE
发明人： MARTIN FRANCOIS
IPC分类号： C23C16/30 , C23C16/40 , C30B25/02 , B05D5/12 , C01B4/00 , C23C16/34

10. 发明专利

FR2810791A1 Preparation of a coating on a substrate, e.g. metal oxides on silicon-based substrates, involves chemical atomic layer deposition using a deuterated reactant 未知
公开(公告)号：FR2810791A1
公开(公告)日：2001-12-28
申请号：FR0007932
申请日：2000-06-21
申请人： COMMISSARIAT ENERGIE ATOMIQUE
发明人： MARTIN FRANCOIS , MUR PIERRE , BARON THIERRY
IPC分类号： C23C16/30 , C23C16/40 , C23C16/44 , C30B25/02 , H01L21/3205 , H01L21/324
摘要： A layer of at least one metal or a deuterated compound of at least one metal is deposited on a substrate by chemical atomic layer deposition (ALD) using at least a non-deuterated precursor of the metal or metal compound and a deuterated reagent, which, for a silicon substrate, avoids the growth of parasitic SiO2 under a layer of, e.g., a high-K dielectric metal oxide. Preferred Features: The substrate is selected from pure Si, SiGe, SiC, polycrystalline silicon and substrates having an ALD-deposited monolayer of a compound selected from MoSi2, MoGe2, MoSixNy, and MoGexNy, starting from deuterated reactants such as SiD4, GeD4 and ND3. The metal is selected from Hf, Zr, Ti, Nb, Mo, W, Ta, Al, Mg, Si and Ge. The metal compound is selected from oxides, nitrides, germanides, silicides and ternary compounds of the metal with Si, or Ge and N. The deuterated reactant is selected from heavy water (D2O), D2O2, ND3, SiD4 and GeD4. Deposition is carried out at 500 degrees C or lower, preferably 200-400 degrees C, and the coating can comprise a single layer or many layers. The deuterated compound of at least one metal is a deuterated oxide of a metal having higher electropositivity than Si, such as Al or Mg. Preferably, the deuterated oxide is a mixed oxide of Al or Mg and another metal having lower electropositivity than Mg, such as Hf, or it can be a high permittivity (High-K) oxide, and it is impermeable to hydrogen. The metal oxide can be selected from oxides of Al, Ti, Zr and Hf and oxides having greater permittivity than that of SiO2. A layer of metal selected from Mo, Ti, Ta and Nb can be deposited on the deuterated metal oxide layer by ALD using a chlorinated or brominated metal precursor and the deuterated reagent.

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