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1. 发明授权

US07507994B2 Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07507994B2
公开(公告)日：2009-03-24
申请号：US11625694
申请日：2007-01-22
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Hao , Jong-Soo Yoon , Doug-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Hao , Jong-Soo Yoon , Doug-Gyu Kim
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。

2. 发明申请

US20070126005A1 THIN FILM TRANSISTOR ARRAY PANELS FOR A LIQUID CRYSTAL DISPLAY AND A METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列及其制造方法
公开(公告)号：US20070126005A1
公开(公告)日：2007-06-07
申请号：US11625694
申请日：2007-01-22
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Doug-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Doug-Gyu Kim
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。

3. 发明授权

US07176496B2 Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07176496B2
公开(公告)日：2007-02-13
申请号：US11080612
申请日：2005-03-16
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Hao , Jong-Soo Yoon , Dong-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Hao , Jong-Soo Yoon , Dong-Gyu Kim
IPC分类号： H01L29/04 , H01L29/15 , H01L31/36
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

4. 发明申请

US20050170592A1 Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20050170592A1
公开(公告)日：2005-08-04
申请号：US11080612
申请日：2005-03-16
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
IPC分类号： G02F1/1362 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/49 , H01L31/0376
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

5. 发明授权

US06524876B1 Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US06524876B1
公开(公告)日：2003-02-25
申请号：US09545891
申请日：2000-04-07
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
IPC分类号： H01L2100
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

6. 发明授权

US06887742B2 Method for manufacturing a thin film transistor array panel for a liquid crystal display 有权
标题翻译：制造液晶显示器用薄膜晶体管阵列面板的方法
公开(公告)号：US06887742B2
公开(公告)日：2005-05-03
申请号：US10302927
申请日：2002-11-25
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
IPC分类号： G02F1/1362 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/49 , H01L21/00 , H01L21/337
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积并图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

7. 发明授权

US06849873B2 Thin film transistor array panel for a liquid crystal display 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板
公开(公告)号：US06849873B2
公开(公告)日：2005-02-01
申请号：US10303016
申请日：2002-11-25
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
IPC分类号： G02F1/1362 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/04
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： In liquid crystal display device having a multi-layer conductive layer, such conductive layer is formed using a photoresist pattern having different thicknesses depending on the position. Upper layer of the gate pad is removed using an etch mask of the photoresist pattern of different thickness. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire. Finally passivation layer is formed and an indium tin oxide layer is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad.
摘要翻译：在具有多层导电层的液晶显示装置中，使用根据位置具有不同厚度的光致抗蚀剂图案形成这种导电层。使用不同厚度的光致抗蚀剂图案的蚀刻掩模去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成数据线。最后，形成钝化层，并且沉积和图案化氧化铟锡层以形成像素电极，冗余栅极焊盘和冗余数据焊盘。

8. 发明授权

US06307216B1 Thin film transistor panels for liquid crystal displays 有权
标题翻译：用于液晶显示器的薄膜晶体管面板
公开(公告)号：US06307216B1
公开(公告)日：2001-10-23
申请号：US09533379
申请日：2000-03-22
申请人： Sung-Wook Huh , Mun-Pyo Hong , Jang-Soo Kim , Bum-Ki Baek
发明人： Sung-Wook Huh , Mun-Pyo Hong , Jang-Soo Kim , Bum-Ki Baek
IPC分类号： H01L2904
CPC分类号： G02F1/1309 , G02F2001/136263 , G02F2001/136272 , H01L27/124
摘要： Disclosed are ring-shaped gate wires and redundancy lines formed on a substrate so that defects due to disconnection of data lines can be readily repaired. The redundancy line is formed in a unit of a pixel, located outside the gate wire and divided into two portions. A gate insulating film is formed thereon, and data lines are formed thereon. Each of the data line overlaps the redundancy line and intersects a portion of the gate wire. A passivation film is formed on the data lines and transparent conductive connect patterns are formed thereon. The transparent connect pattern intersects two adjacent pixels and overlaps the ends of the redundancy lines facing each other. Since the end portions of the redundancy lines are bent out from the direction of the data line, it is not required that the connect pattern overlaps the data line. When the data line is disconnected on the step point where the data line intersects the gate wire, the redundancy lines can be short-circuited to the data line on either side of the disconnection point by using a laser to repair the disconnection.
摘要翻译：公开了形成在基板上的环形栅极线和冗余线，从而可以容易地修复由于数据线断开引起的缺陷。冗余线形成为位于栅极线外侧的像素单位，并分成两部分。在其上形成栅极绝缘膜，并在其上形成数据线。每条数据线与冗余线重叠，并与栅极线的一部分相交。在数据线上形成钝化膜，并在其上形成透明导电连接图案。透明连接图案与两个相邻的像素相交并且与彼此面对的冗余线的端部重叠。由于冗余线的端部从数据线的方向弯曲，所以不需要连接图案与数据线重叠。当数据线在数据线与栅极线相交的步进点上断开数据线时，冗余线可以通过使用激光修复断线而与断开点两侧的数据线短路。

9. 发明授权

US07504290B2 Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same 有权
标题翻译：一种用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07504290B2
公开(公告)日：2009-03-17
申请号：US11750630
申请日：2007-05-18
申请人： Mun-Pyo Hong , Woon-Yong Park , Jong-Soo Yoon
发明人： Mun-Pyo Hong , Woon-Yong Park , Jong-Soo Yoon
IPC分类号： H01L21/84
CPC分类号： G02F1/13458 , G02F1/1362 , G02F1/136227 , G02F2001/136236 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/458 , Y10S438/942 , Y10S438/947 , Y10S438/949
摘要： Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.
摘要翻译：制造液晶显示器的简化方法。通过使用第一掩模在基板上形成包括栅极线，栅极焊盘和栅电极的栅极线。依次沉积栅极绝缘层，半导体层，欧姆接触层和金属层以制成四层，并通过使用第二掩模的干蚀刻图案化。此时，四层被图案化以具有网状布局的矩阵并覆盖栅极线。在显示区域形成露出基板的开口，在周边区域形成露出栅极焊盘的接触孔。接下来，沉积ITO并且涂覆在ITO上的光致抗蚀剂层。然后，通过使用第三掩模和干蚀刻对ITO层进行图案化，并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。在沉积钝化层之后，通过使用第四掩模形成开口，并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。

10. 发明申请

US20060228821A1 Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same 审中-公开
公开(公告)号：US20060228821A1
公开(公告)日：2006-10-12
申请号：US11451686
申请日：2006-06-13
申请人： Mun-Pyo Hong , Woon-Yong Park , Jong-Soo Yoon
发明人： Mun-Pyo Hong , Woon-Yong Park , Jong-Soo Yoon
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： G02F1/13458 , G02F1/1362 , G02F1/136227 , G02F2001/136236 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/458 , Y10S438/942 , Y10S438/947 , Y10S438/949
摘要： Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

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