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1. 发明授权

US6128674A Method of minimizing host CPU utilization in driving an adapter by residing in system memory a command/status block a soft interrupt block and a status block queue 失效
标题翻译：通过驻留在系统存储器中来最小化驱动适配器的主机CPU利用率的方法，命令/状态块软中断块和状态块队列
公开(公告)号：US6128674A
公开(公告)日：2000-10-03
申请号：US908888
申请日：1997-08-08
申请人： Bruce Leroy Beukema , Patrick Allen Buckland , Wen-Tzer Thomas Chen , David Arlen Elko , Ian David Judd , Renato John Recio
发明人： Bruce Leroy Beukema , Patrick Allen Buckland , Wen-Tzer Thomas Chen , David Arlen Elko , Ian David Judd , Renato John Recio
IPC分类号： G06F3/00 , G06F9/06 , G06F12/08 , G06F13/28
CPC分类号： G06F12/0835
摘要： The system I/O interface and its data structure are designed to minimize the host CPU utilization in driving an adapter. The interface is also designed to reduce the system interference in processing I/O requests. To eliminate the need of using PIO instructions, the command/status blocks for exchanging messages between the system and the adapter reside in the system memory. The data structure is designed to avoid "share write" entries in order to further minimize the overhead of maintaining each coherency when updating an entry in the cache either concurrently or sequentially by both adapter and system CPU. Further, the data structure of the control and status blocks is resided in the system memory. The system CPU uses STORE instruction to prepare control blocks and LOAD instruction to read from completion status blocks; while the adapter will rely on its DMA engine to move data to/from system memory in accessing control/status blocks.
摘要翻译：系统I / O接口及其数据结构旨在最大限度地减少驱动适配器时的主机CPU利用率。该接口还旨在减少处理I / O请求时的系统干扰。为了不需要使用PIO指令，系统和适配器之间交换消息的命令/状态块驻留在系统内存中。数据结构旨在避免“共享写入”条目，以便在适配器和系统CPU同时或顺序更新缓存中的条目时进一步最小化维护每个一致性的开销。此外，控制和状态块的数据结构驻留在系统存储器中。系统CPU使用STORE指令准备控制块和LOAD指令，从完成状态块读取; 而适配器将依靠其DMA引擎在访问控制/状态块时将数据移入/移出系统内存。

2. 发明授权

US06467022B1 Extending adapter memory with solid state disks in JBOD and RAID environments 失效
标题翻译：在JBOD和RAID环境中扩展具有固态硬盘的适配器内存
公开(公告)号：US06467022B1
公开(公告)日：2002-10-15
申请号：US09706111
申请日：2000-11-03
申请人： Pat Allen Buckland , Ian David Judd , Gary Robert Lyons , Renato John Recio , Michael Francis Scully
发明人： Pat Allen Buckland , Ian David Judd , Gary Robert Lyons , Renato John Recio , Michael Francis Scully
IPC分类号： G06F1208
CPC分类号： G06F3/0656 , G06F3/0611 , G06F3/068 , G06F3/0689 , G06F11/1076 , G06F12/0866 , G06F2211/1009 , G06F2211/1054 , G06F2212/2022 , G06F2212/312
摘要： A Solid State Disk (“SSD”) and accompanying logic to extend the local memory of an adapter for RAID storage devices. Use of virtual memory, representing the SSD range of addresses in the adapter address memory, allows the adapter to incorporate the total memory into the adapter memory structure. The SSD is non-volatile and large amounts of cache items may be transferred to the SSD as an extension of the adapter memory. The cache write may be delayed and subsequently written to a designated address on a RAID drive, freeing the adapter on-board memory and control functions. Further, the size of the SSD allows for large amounts of data staging and storage, permitting device-to-device communications that would reduce the read and write commands between the host, adapter and drives.
摘要翻译：固态硬盘（“SSD”）以及用于扩展RAID存储设备适配器的本地内存的随附逻辑。使用虚拟内存，代表适配器地址存储器中的SSD范围的地址，允许适配器将总内存合并到适配器内存结构中。 SSD是非易失性的，并且大量的缓存项可以作为适配器存储器的扩展传送到SSD。高速缓存写入可能被延迟并随后写入RAID驱动器上的指定地址，释放适配器板上存储器和控制功能。此外，SSD的大小允许大量的数据分段和存储，允许设备到设备通信，这将减少主机，适配器和驱动器之间的读取和写入命令。

3. 发明授权

US07092401B2 Apparatus and method for managing work and completion queues using head and tail pointers with end-to-end context error cache for reliable datagram 失效
标题翻译：用于使用具有端到端上下文错误缓存的头尾指针来管理工作和完成队列的装置和方法，用于可靠的数据报
公开(公告)号：US07092401B2
公开(公告)日：2006-08-15
申请号：US09999144
申请日：2001-11-15
申请人： David F. Craddock , Thomas Anthony Gregg , Ian David Judd , Gregory Francis Pfister , Renato John Recio
发明人： David F. Craddock , Thomas Anthony Gregg , Ian David Judd , Gregory Francis Pfister , Renato John Recio
IPC分类号： H04L12/28 , H04L12/56 , H04L12/54
CPC分类号： H04L49/901 , H04L12/2801 , H04L49/90 , H04L49/9057
摘要： An apparatus and method for managing reliable datagram work queues, and associated completion queues, using head and tail pointers with end-to-end context error cache are provided. Reliable datagram (RD) queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a RD queue page table index and a RD queue page index for identifying a position within the RD queue. For RD work queues, in the channel interface, the tail pointer is used to identify a next position where a work queue entry may be written and the head pointer is used only to determine whether the work queue is full. In the host channel adapter, the head pointer is used to identify a next work queue entry for processing and the tail pointer is used to determine if the queue is empty.
摘要翻译：提供了一种用于使用具有端到端上下文错误高速缓存的头和尾指针来管理可靠数据报工作队列和相关联的完成队列的装置和方法。在通道接口和主机通道适配器中维护可靠的数据报（RD）队列头尾指针。主机通道适配器中的头和尾指针包括RD队列页表索引和用于标识RD队列中的位置的RD队列页索引。对于RD工作队列，在通道接口中，尾部指针用于标识可以写入工作队列条目的下一个位置，而头部指针仅用于确定工作队列是否已满。在主机通道适配器中，头指针用于标识用于处理的下一个工作队列条目，并且尾部指针用于确定队列是否为空。

4. 发明授权

US06789143B2 Infiniband work and completion queue management via head and tail circular buffers with indirect work queue entries 失效
标题翻译： Infiniband通过头尾循环缓冲区进行工作和完成队列管理，间接工作队列条目
公开(公告)号：US06789143B2
公开(公告)日：2004-09-07
申请号：US09961922
申请日：2001-09-24
申请人： David F. Craddock , Thomas Anthony Gregg , Ian David Judd , Gregory Francis Pfister , Renato John Recio , Donald William Schmidt
发明人： David F. Craddock , Thomas Anthony Gregg , Ian David Judd , Gregory Francis Pfister , Renato John Recio , Donald William Schmidt
IPC分类号： G06F1300
CPC分类号： G06F9/546
摘要： A distributed computing system having (host and I/O) end nodes, switches, routers, and links interconnecting these components is provided. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes use completion queues to inform the end user when a message has been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism implements these queue pairs and completion queues in hardware. A mechanism for controlling the transfer of work requests from the consumer to the CA hardware and work completions from the CA hardware to the consumer using head and tail pointers that reference circular buffers is also provided. The QPs and CQs do not contain Work Queue Entries and Completion Queue Entries respectively, but instead contain references to these entries. This allows them to be efficient and constant in size, while the Work Queue Entries and Completion Queue Entries themselves can vary in size, for example to include a variable number of data segments. Additionally, several mechanisms are provided to improve the overall efficiency of this process under different memory configurations.
摘要翻译：提供了具有（主机和I / O）端节点，交换机，路由器和互连这些组件的链路的分布式计算系统。终端节点使用发送和接收队列对来发送和接收消息。终端节点使用完成队列通知终端用户何时完全发送或接收了消息，以及在消息发送或接收过程中是否发生错误。机制在硬件中实现这些队列对和完成队列。还提供了一种机制，用于控制从消费者到CA硬件的工作请求的传送以及使用引用循环缓冲区的头和尾指针从CA硬件到消费者的完成。 QP和CQ不分别包含工作队列条目和完成队列条目，而是包含对这些条目的引用。这允许它们在高度和大小上是恒定的，而工作队列条目和完成队列条目本身可以在大小上变化，例如包括可变数量的数据段。另外，提供了几种机制以在不同的存储器配置下提高该过程的整体效率。

5. 发明授权

US06725296B2 Apparatus and method for managing work and completion queues using head and tail pointers 失效
标题翻译：使用头部和尾部指针管理工作和完成队列的装置和方法
公开(公告)号：US06725296B2
公开(公告)日：2004-04-20
申请号：US09915663
申请日：2001-07-26
申请人： David F. Craddock , Thomas Anthony Gregg , Ian David Judd , Gregory Francis Pfister , Renato John Recio , Donald William Schmidt
发明人： David F. Craddock , Thomas Anthony Gregg , Ian David Judd , Gregory Francis Pfister , Renato John Recio , Donald William Schmidt
IPC分类号： G06F300
CPC分类号： G06F9/4806
摘要： An apparatus and method for managing work and completion queues using head and tail circular pointers. With the apparatus and method, queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a queue pointer table index and a queue page index for identifying a position within the queue. For work queues, the tail pointer in the channel interface is used to identify a next position where a work queue entry may be written. The head pointer in the channel interface is used only to determine whether the work queue is full or not. The head pointer in the host channel adapter is used to identify a next work queue entry for processing by the host channel adapter. The tail pointer in the host channel adapter is used by the host channel adapter to determine if the queue is empty. For completion queues, the head pointer in the channel interface is used to identify a next completion queue entry to be processed. The tail pointer in the host channel adapter is used to identify a next position in the completion queue to which the host channel adapter may post a completion queue entry.
摘要翻译：一种使用头尾循环指针管理工作和完成队列的装置和方法。使用设备和方法，在通道接口和主机通道适配器中维护队列头尾指针。主机通道适配器中的头和尾指针包括队列指针表索引和用于标识队列中的位置的队列页索引。对于工作队列，通道接口中的尾部指针用于标识可以写入工作队列条目的下一个位置。通道接口中的头指针仅用于确定工作队列是否已满。主机通道适配器中的头指针用于标识下一个工作队列条目以供主机通道适配器处理。主机通道适配器中的尾部指针由主机通道适配器使用，以确定队列是否为空。对于完成队列，通道接口中的头指针用于标识要处理的下一个完成队列条目。主机通道适配器中的尾部指针用于标识完成队列中的下一个位置，主机通道适配器可以向其发布完成队列条目。

6. 发明授权

US09043543B2 Writing of new data of a first block size in a raid array that stores both parity and data in a second block size 有权
公开(公告)号：US09043543B2
公开(公告)日：2015-05-26
申请号：US13113546
申请日：2011-05-23
申请人： Michael T. Benhase , Ian David Judd , Daniel F. Moertl , Karl A. Nielsen
发明人： Michael T. Benhase , Ian David Judd , Daniel F. Moertl , Karl A. Nielsen
IPC分类号： G06F12/00 , G06F3/06 , G06F11/20 , G11B20/12 , G06F11/10
CPC分类号： G06F3/061 , G06F3/0638 , G06F3/0661 , G06F3/0689 , G06F11/1076 , G06F11/2089 , G06F2211/1057 , G06F2211/1059 , G11B2020/1222 , G11B2220/415
摘要： A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.

7. 发明申请

US20120303890A1 WRITING OF NEW DATA OF A FIRST BLOCK SIZE IN A RAID ARRAY THAT STORES BOTH PARITY AND DATA IN A SECOND BLOCK SIZE 有权
公开(公告)号：US20120303890A1
公开(公告)日：2012-11-29
申请号：US13113546
申请日：2011-05-23
申请人： Michael T. Benhase , Ian David Judd , Daniel F. Moertl , Karl A. Nielsen
发明人： Michael T. Benhase , Ian David Judd , Daniel F. Moertl , Karl A. Nielsen
IPC分类号： G06F12/16
CPC分类号： G06F3/061 , G06F3/0638 , G06F3/0661 , G06F3/0689 , G06F11/1076 , G06F11/2089 , G06F2211/1057 , G06F2211/1059 , G11B2020/1222 , G11B2220/415
摘要： A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.

8. 发明申请

US20100204935A1 CONNECTION ERROR AVOIDANCE FOR APPARATUS CONNECTED TO A POWER SUPPLY 有权
标题翻译：连接到电源的设备的连接错误避免
公开(公告)号：US20100204935A1
公开(公告)日：2010-08-12
申请号：US12766664
申请日：2010-04-23
申请人： Steven John Hyatt , Ian David Judd , Robert Bruce Nicholson , Paul Jonathan Quelch , Stephen Arthur Randle , William James Scales
发明人： Steven John Hyatt , Ian David Judd , Robert Bruce Nicholson , Paul Jonathan Quelch , Stephen Arthur Randle , William James Scales
IPC分类号： G06F19/00 , G01R21/00
CPC分类号： G06F11/2289 , Y10T307/615
摘要： According to one general embodiment of the present invention, there is provided a computer program product for reducing incidence of errors in connections between a power consumer apparatus operable to draw a load and a power supply apparatus capable of varying the power supplied, the computer program product comprising: a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising: computer readable program code configured to generate at the power consumer apparatus an identifiable pattern in a load to be drawn from a power supply connection to a power supply apparatus; and computer readable program code configured to monitor at the power consumer apparatus for a change in the load corresponding to the pattern, the monitoring being performed across a signal connection to the power supply apparatus; wherein a positive result of the monitoring indicates a correct configuration. Additional embodiments are also presented.
摘要翻译：根据本发明的一个一般实施例，提供了一种用于减少可操作以绘制负载的电力消耗装置与能够改变供电的电源装置之间的连接中的错误的发生率的计算机程序产品，该计算机程序产品该计算机可读程序代码包括：计算机可读程序代码，其被配置为在电力消费者设备处生成要从电源连接抽取到的负载中的可识别模式电源设备; 以及计算机可读程序代码，被配置为在所述用电设备处监视对应于所述模式的负载的变化，所述监视是通过与所述电源装置的信号连接进行的; 其中监视的肯定结果指示正确的配置。还提供了另外的实施例。

9. 发明授权

US07380198B2 System and method for detecting write errors in a storage device 有权
标题翻译：用于检测存储设备中写入错误的系统和方法
公开(公告)号：US07380198B2
公开(公告)日：2008-05-27
申请号：US10839106
申请日：2004-05-05
申请人： Ian David Judd
发明人： Ian David Judd
IPC分类号： G11C29/00 , G11C7/00 , H03M13/00
CPC分类号： G11B20/18 , G06F11/1076 , G06F2211/1059
摘要： A system for detecting write errors in a storage device is disclosed. The system comprises a storage device; within the storage device, means for storing one or more data blocks in a storage group, the storage group comprising the one or more data blocks and a check block, wherein the check block comprises one of the group of: a combination of the one or more data blocks of the storage group, a combination of one or more bits of a logical block address associated with the storage group, and a combination of one or more bits of a phase field that is updated each time the storage group is written; means for updating the check block each time the storage group is written; and means for detecting write errors by checking the check block.
摘要翻译：公开了一种用于检测存储装置中的写入错误的系统。该系统包括存储装置; 在所述存储设备内，用于将一个或多个数据块存储在存储组中的装置，所述存储组包括所述一个或多个数据块和校验块，其中所述校验块包括以下组中的一个：所述一个或多个存储组的更多数据块，与存储组相关联的逻辑块地址的一个或多个位的组合，以及每次存储组被写入时更新的相位字段的一个或多个位的组合; 每次存储组写入时更新检查块的装置; 以及用于通过检查检查块来检测写入错误的装置。

10. 发明授权

US6038618A Bypass circuit for bypassing host computer which are connected to plurality of devices via two individual ports upon detecting lack of communication at both ports 失效
标题翻译：旁路电路，用于在检测到两个端口上的通信不足时，经由两个单独端口连接到多个设备的主机
公开(公告)号：US6038618A
公开(公告)日：2000-03-14
申请号：US907580
申请日：1997-08-08
申请人： Reginald Beer , Peter John Deacon , Ian David Judd , Neil Morris
发明人： Reginald Beer , Peter John Deacon , Ian David Judd , Neil Morris
IPC分类号： H04L12/437 , C06F11/22
CPC分类号： H04L12/437
摘要： A data processing system comprises a host computer connected for the transfer of data to and from a plurality of data storage devices arranged in a string, the host computer including communication means comprising first and second ports connecting to first and second communication links, the first and second communication links being connected respectively to first and second data storage devices of said string. A bypassing means is provided between the first and second ports of the host system and the first and second data storage devices, the bypassing means being comprised of an independent bypass circuit on each of the first and second communication links between each of the first and second ports and the first and second data storage devices, the bypassing means being operable to bypass the host computer by connecting the first and second devices only when both of said independent bypass circuits detect a lack of data transfer on their respective links.
摘要翻译：一种数据处理系统包括连接到用于将数据传送到排列在一串中的多个数据存储设备的主计算机，该主计算机包括通信装置，该通信装置包括连接到第一和第二通信链路的第一和第二端口，第一和第二通信链路第二通信链路分别连接到所述串的第一和第二数据存储设备。旁路装置设置在主机系统的第一和第二端口与第一和第二数据存储装置之间，旁路装置包括在第一和第二通信链路中的每个第一和第二通信链路之间的独立旁路电路端口和第一和第二数据存储设备，旁路装置可操作以仅在两个独立旁路电路检测到其各自链路上的数据传输不足时才通过连接第一和第二设备来绕过主计算机。

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