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1. 发明授权

US07105903B2 Methods and structures for electrical communication with an overlying electrode for a semiconductor element 有权
标题翻译：用于与半导体元件的上覆电极电连通的方法和结构
公开(公告)号：US07105903B2
公开(公告)日：2006-09-12
申请号：US10993196
申请日：2004-11-18
申请人： Brian R. Butcher , Gregory W. Grynkewich , Kelly W. Kyler , Kenneth H. Smith , Richard G. Williams
发明人： Brian R. Butcher , Gregory W. Grynkewich , Kelly W. Kyler , Kenneth H. Smith , Richard G. Williams
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L29/82 , H01L43/00
CPC分类号： H01L43/12 , H01L27/226
摘要： Structures for electrical communication with an overlying electrode for a semiconductor element and methods for fabricating such structures are provided. The structure for electrical communication with an overlying electrode comprises a first electrode having a lateral dimension, a semiconductor element overlying the first electrode, and a second electrode overlying the semiconductor element. The second electrode has a lateral dimension that is less than the lateral dimension of the first electrode. A conductive hardmask overlies the second electrode and is in electrical communication with the second electrode. The conductive hardmask has a lateral dimension that is substantially equal to the lateral dimension of the first electrode. A conductive contact element is in electrical communication with the conductive hardmask.
摘要翻译：提供了用于与半导体元件的上覆电极的电连通的结构以及用于制造这种结构的方法。与上覆电极电连通的结构包括具有横向尺寸的第一电极，覆盖第一电极的半导体元件和覆盖半导体元件的第二电极。第二电极具有小于第一电极的横向尺寸的横向尺寸。导电硬掩模覆盖在第二电极上并且与第二电极电连通。导电硬掩模具有基本上等于第一电极的横向尺寸的横向尺寸。导电接触元件与导电硬掩模电连通。

2. 发明授权

US06518071B1 Magnetoresistive random access memory device and method of fabrication thereof 失效
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US06518071B1
公开(公告)日：2003-02-11
申请号：US10109429
申请日：2002-03-28
申请人： Mark A. Durlam , Mark F. Deherrera , Kelly W. Kyler , Brian R. Butcher , Gregory W. Grynkewich , Steven M. Smith , Charles Snyder , Jon M. Slaughter
发明人： Mark A. Durlam , Mark F. Deherrera , Kelly W. Kyler , Brian R. Butcher , Gregory W. Grynkewich , Steven M. Smith , Charles Snyder , Jon M. Slaughter
IPC分类号： H01L2100
CPC分类号： H01L43/12
摘要： A method of fabricating a MRAM device with a taper comprising the steps of providing a substrate, forming a dielectric region with positioned on the substrate, patterning and isotropically etching through the dielectric region to the substrate to form a trench, depositing the MRAM device within the trench wherein the MRAM device includes a first ferromagnetic region with a width positioned on the substrate, a non-ferromagnetic spacer layer with a width positioned on the first ferromagnetic region, and a second ferromagnetic region with a width positioned on the non-ferromagnetic spacer layer wherein the taper is formed by making the width of the first ferromagnetic region greater than the width of the non-ferromagnetic spacer layer, and the width of the non-ferromagnetic spacer layer greater than the width of the second ferromagnetic region so that the first ferromagnetic region is separated from the second ferromagnetic region.
摘要翻译：一种制造具有锥形的MRAM器件的方法，包括以下步骤：提供衬底，形成位于衬底上的电介质区域，对介质区域进行图案化和各向同性地蚀刻到衬底以形成沟槽，将MRAM器件沉积在沟槽，其中MRAM器件包括位于衬底上的宽度的第一铁磁区域，具有位于第一铁磁区域上的宽度的非铁磁间隔层，以及位于非铁磁间隔层上的宽度的第二铁磁区域其中所述锥形通过使所述第一铁磁性区域的宽度大于所述非铁磁间隔层的宽度而形成，并且所述非铁磁隔离层的宽度大于所述第二铁磁区域的宽度，使得所述第一铁磁性区域区域与第二铁磁区域分离。

3. 发明授权

US07105363B2 Cladded conductor for use in a magnetoelectronics device and method for fabricating the same 失效
标题翻译：用于磁电子器件的包层导体及其制造方法
公开(公告)号：US07105363B2
公开(公告)日：2006-09-12
申请号：US11082617
申请日：2005-03-16
申请人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
发明人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
IPC分类号： H01L21/00
CPC分类号： H01L27/222 , G11C11/15 , H01L28/10 , H01L43/12
摘要： A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
摘要翻译：提供一种用于制造用于磁电装置的包层导体（42）的方法。该方法包括提供衬底（10）并形成覆盖衬底（10）的导电阻挡层（12）。形成在导电阻挡层（12）上方的电介质层（16），并且在电介质层（16）的一部分内形成导电线（20）。去除电介质层（16），并且形成覆盖导线（20）的集流器（30）。

4. 发明授权

US06885074B2 Cladded conductor for use in a magnetoelectronics device and method for fabricating the same 有权
标题翻译：用于磁电子器件的包层导体及其制造方法
公开(公告)号：US06885074B2
公开(公告)日：2005-04-26
申请号：US10306250
申请日：2002-11-27
申请人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
发明人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
IPC分类号： G11C11/15 , H01L21/02 , H01L27/22 , H01L43/12 , H01L29/82 , H01L27/14
CPC分类号： H01L27/222 , G11C11/15 , H01L28/10 , H01L43/12
摘要： A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
摘要翻译：提供一种用于制造用于磁电装置的包层导体（42）的方法。该方法包括提供衬底（10）并形成覆盖衬底（10）的导电阻挡层（12）。形成在导电阻挡层（12）上方的电介质层（16），并且在电介质层（16）的一部分内形成导电线（20）。去除电介质层（16），并且形成覆盖导线（20）的集流器（30）。

5. 发明授权

US07445943B2 Magnetic tunnel junction memory and method with etch-stop layer 有权
标题翻译：磁隧道结记忆和具有蚀刻停止层的方法
公开(公告)号：US07445943B2
公开(公告)日：2008-11-04
申请号：US11584411
申请日：2006-10-19
申请人： Kenneth H. Smith , Brian R. Butcher , Gregory W. Grynkewich , Srinivas V. Pietambaram , Nicholas D. Rizzo
发明人： Kenneth H. Smith , Brian R. Butcher , Gregory W. Grynkewich , Srinivas V. Pietambaram , Nicholas D. Rizzo
IPC分类号： H01L21/00
CPC分类号： H01L43/12
摘要： Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204). In a further embodiment, a second etch-stop layer (90, 250) is located between the second electrode (66, 236) and the second write conductor (92, 260). Improved yield and performance are obtained.
摘要翻译：提供了采用磁隧道结（MTJ）的磁阻存储器的方法和装置。该装置包括MTJ（61,231），第一（60,220）和第二（66,236）电极，其分别耦合到MTJ（61）的第一（62,232）和第二（64,234）磁性层，231），第一（54,204）和第二（92,260）写入导体，其磁耦合到MTJ（61,231）并且与第一（60,220）和第二（66,236）电极间隔开，以及位于所述第一写入导体（54,204）和所述第一电极（60,220）之间的至少一个蚀刻停止层（82,216）具有用于蚀刻所述MTJ（61,231）的试剂中的蚀刻速率和 /或第一电极（60,220），其至多为MTJ（61,231）和/或第一导体（60,220）的蚀刻速率的25％的相同试剂，以便允许部分 MTJ（61,231）和第一电极（60,220）被去除而不影响下面的第一写入导体（54,204）。在另一实施例中，第二蚀刻停止层（90,250）位于第二电极（66,236）和第二写入导体（92,260）之间。获得了提高的产量和性能。

6. 发明授权

US07279341B2 Method for fabricating a flux concentrating system for use in a magnetoelectronics device 失效
标题翻译：制造用于磁电装置的通量集中系统的方法
公开(公告)号：US07279341B2
公开(公告)日：2007-10-09
申请号：US11125955
申请日：2005-05-09
申请人： Thomas V. Meixner , Gregory W. Grynkewich , Jaynal A. Molla , J. Jack Ren , Richard G. Williams , Brian R. Butcher , Mark A. Durlam
发明人： Thomas V. Meixner , Gregory W. Grynkewich , Jaynal A. Molla , J. Jack Ren , Richard G. Williams , Brian R. Butcher , Mark A. Durlam
IPC分类号： H01L21/465
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/16 , H01L43/12
摘要： A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
摘要翻译：提供了一种用于制造用于磁电装置的通量集中系统（62）的方法。该方法包括以下步骤：提供在衬底（12）中形成的位线（10），并形成覆盖位线（10）和衬底（12）的第一材料层（24）。进行蚀刻以在第一材料层（24）中形成沟槽（58），并且在沟槽（52）中沉积包层（56）。缓冲材料层（58）形成在覆层（56）上，缓冲材料层（58）的一部分和包覆层（56）的一部分被去除。

7. 发明授权

US06943038B2 Method for fabricating a flux concentrating system for use in a magnetoelectronics device 有权
标题翻译：制造用于磁电装置的通量集中系统的方法
公开(公告)号：US06943038B2
公开(公告)日：2005-09-13
申请号：US10324716
申请日：2002-12-19
申请人： Thomas V. Meixner , Gregory W. Grynkewich , Jaynal A. Molla , J. Jack Ren , Richard G. Williams , Brian R. Butcher , Mark A. Durlam
发明人： Thomas V. Meixner , Gregory W. Grynkewich , Jaynal A. Molla , J. Jack Ren , Richard G. Williams , Brian R. Butcher , Mark A. Durlam
IPC分类号： G11C11/16 , H01L21/8246 , H01L21/00
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/16 , H01L43/12
摘要： A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
摘要翻译：提供了一种用于制造用于磁电装置的通量集中系统（62）的方法。该方法包括以下步骤：提供在衬底（12）中形成的位线（10），并形成覆盖位线（10）和衬底（12）的第一材料层（24）。进行蚀刻以在第一材料层（24）中形成沟槽（58），并且在沟槽（52）中沉积包层（56）。缓冲材料层（58）形成在覆层（56）上，缓冲材料层（58）的一部分和包覆层（56）的一部分被去除。

8. 发明授权

US06911156B2 Methods for fabricating MRAM device structures 有权
标题翻译：制造MRAM器件结构的方法
公开(公告)号：US06911156B2
公开(公告)日：2005-06-28
申请号：US10417537
申请日：2003-04-16
申请人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Kenneth H. Smith , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Kenneth H. Smith , Clarence J. Tracy
IPC分类号： G11B5/127 , G11C11/16 , H01L21/00 , H01L43/12 , H04R31/00 , H05K3/02
CPC分类号： G11C11/16 , H01L43/12 , Y10T29/49041 , Y10T29/49044 , Y10T29/49156 , Y10T29/49165
摘要： A method for fabricating a magnetic memory element structure comprises providing a dielectric layer having a conducting via. A first magnetic layer is formed overlying the dielectric layer and is in electrical communication with the conducting via. A non-magnetic layer and a second magnetic layer are formed overlying the first magnetic layer. A first conductive layer is deposited overlying the second magnetic layer and is patterned. A portion of the second magnetic layer is exposed and is transformed to form an inactive portion and an active portion. The active portion comprises a portion of a memory element and the inactive portion comprises an insulator. A sidewall spacer is formed about at least one sidewall of the first conductive layer and a masking tab is formed that overlies a portion of the memory element and extends to overlie at least a portion of the conducting via.
摘要翻译：一种用于制造磁存储元件结构的方法，包括提供具有导电通孔的电介质层。第一磁性层形成在电介质层上并与导电通孔电连通。在第一磁性层上形成非磁性层和第二磁性层。将第一导电层沉积在第二磁性层上并被图案化。第二磁性层的一部分被暴露并被变换以形成非活性部分和活性部分。有源部分包括存储元件的一部分，非活性部分包括绝缘体。围绕第一导电层的至少一个侧壁形成侧壁间隔物，并且形成覆盖存储元件的一部分并延伸以覆盖导电通孔的至少一部分的掩蔽突片。

9. 发明授权

US07476329B2 Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices 有权
标题翻译：用于接触覆盖MRAM器件的电磁元件的导电层的方法
公开(公告)号：US07476329B2
公开(公告)日：2009-01-13
申请号：US11050191
申请日：2005-02-02
申请人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Charles A. Synder , Kenneth H. Smith , Clarence J. Tracy , Richard Williams
发明人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Charles A. Synder , Kenneth H. Smith , Clarence J. Tracy , Richard Williams
IPC分类号： H01L21/00
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/15 , H01L43/12
摘要： A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
摘要翻译：用于使覆盖磁电元件的导电层接触的方法包括形成覆盖电介质区域的存储元件层。沉积在存储元件层上的第一导电层。第一电介质层沉积在第一导电层上，并被图案化和蚀刻以形成第一掩模层。使用第一掩模层，蚀刻第一导电层。沉积第二介电层，覆盖第一掩模层和电介质区域。去除第二介电层的一部分以露出第一掩模层。对第二介电层和第一掩模层进行蚀刻化学处理，使得以比第二介电层更快的速率蚀刻第一掩模层。蚀刻暴露第一导电层。

10. 发明申请

US20080096290A1 Magnetic tunnel junction memory and method with etch-stop layer 有权
标题翻译：磁隧道结记忆和具有蚀刻停止层的方法
公开(公告)号：US20080096290A1
公开(公告)日：2008-04-24
申请号：US11584411
申请日：2006-10-19
申请人： Kenneth H. Smith , Brian R. Butcher , Gregory W. Grynkewich , Srinivas V. Pietambaram , Nicholas D. Rizzo
发明人： Kenneth H. Smith , Brian R. Butcher , Gregory W. Grynkewich , Srinivas V. Pietambaram , Nicholas D. Rizzo
IPC分类号： H01L21/00
CPC分类号： H01L43/12
摘要： Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204). In a further embodiment, a second etch-stop layer (90, 250) is located between the second electrode (66, 236) and the second write conductor (92, 260). Improved yield and performance are obtained.
摘要翻译：提供了采用磁隧道结（MTJ）的磁阻存储器的方法和装置。该装置包括MTJ（61,231），第一（60,220）和第二（66,236）电极，其分别耦合到MTJ（61）的第一（62,232）和第二（64,234）磁性层，231），第一（54,204）和第二（92,260）写入导体，其磁耦合到MTJ（61,231）并且与第一（60,220）和第二（66,236）电极间隔开，以及位于所述第一写入导体（54,204）和所述第一电极（60,220）之间的至少一个蚀刻停止层（82,216）具有用于蚀刻所述MTJ（61,231）的试剂中的蚀刻速率和 /或第一电极（60,220），其至多为MTJ（61,231）和/或第一导体（60,220）的蚀刻速率的25％的相同试剂，以便允许部分 MTJ（61,231）和第一电极（60,220）被去除而不影响下面的第一写入导体（54,204）。在另一实施例中，第二蚀刻停止层（90,250）位于第二电极（66,236）和第二写入导体（92,260）之间。获得了提高的产量和性能。

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