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1. 发明授权

US07666751B2 Method of forming a high capacitance diode and structure therefor 有权
标题翻译：形成高容量二极管的方法及其结构
公开(公告)号：US07666751B2
公开(公告)日：2010-02-23
申请号：US11859638
申请日：2007-09-21
申请人： David D. Marreiro , Sudhama C. Shastri , Gordon M. Grivna , Earl D. Fuchs
发明人： David D. Marreiro , Sudhama C. Shastri , Gordon M. Grivna , Earl D. Fuchs
IPC分类号： H01L21/20
CPC分类号： H01L27/0814 , H01L29/8618 , H01L29/93 , Y10S438/963 , Y10S438/983
摘要： In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.
摘要翻译：在一个实施例中，高掺杂半导体沟道形成在相反导电类型的半导体区域中以增加器件的电容。

2. 发明申请

US20090079032A1 METHOD OF FORMING A HIGH CAPACITANCE DIODE AND STRUCTURE THEREFOR 有权
标题翻译：形成高电容二极管及其结构的方法
公开(公告)号：US20090079032A1
公开(公告)日：2009-03-26
申请号：US11859638
申请日：2007-09-21
申请人： David D. Marreiro , Sudhama C. Shastri , Gordon M. Grivna , Earl D. Fuchs
发明人： David D. Marreiro , Sudhama C. Shastri , Gordon M. Grivna , Earl D. Fuchs
IPC分类号： H01L29/93 , H01L21/20
CPC分类号： H01L27/0814 , H01L29/8618 , H01L29/93 , Y10S438/963 , Y10S438/983
摘要： In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.
摘要翻译：在一个实施例中，高掺杂半导体沟道形成在相反导电类型的半导体区域中以增加器件的电容。

3. 发明授权

US07466212B2 Semiconductor filter structure and method of manufacture 有权
标题翻译：半导体滤波器结构及其制造方法
公开(公告)号：US07466212B2
公开(公告)日：2008-12-16
申请号：US11454387
申请日：2006-06-16
申请人： Sudhama Shastri , Ryan Hurley , Yenting Wen , Emily M. Linehan , Mark A. Thomas , Earl D. Fuchs
发明人： Sudhama Shastri , Ryan Hurley , Yenting Wen , Emily M. Linehan , Mark A. Thomas , Earl D. Fuchs
IPC分类号： H03H9/00
CPC分类号： H03H7/0107 , H01F17/0006 , H01F27/40 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H03H7/1766 , H01L2924/00
摘要： In one embodiment, a split well region of one conductivity type is formed in semiconductor substrate of an opposite conductivity type. The split well region forms one plate of a floating capacitor and an electrode of a transient voltage suppression device.
摘要翻译：在一个实施例中，一种导电类型的分裂阱区形成在相反导电类型的半导体衬底中。分裂阱区域形成浮动电容器的一个板和瞬态电压抑制装置的电极。

4. 发明授权

US07105363B2 Cladded conductor for use in a magnetoelectronics device and method for fabricating the same 失效
标题翻译：用于磁电子器件的包层导体及其制造方法
公开(公告)号：US07105363B2
公开(公告)日：2006-09-12
申请号：US11082617
申请日：2005-03-16
申请人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
发明人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
IPC分类号： H01L21/00
CPC分类号： H01L27/222 , G11C11/15 , H01L28/10 , H01L43/12
摘要： A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
摘要翻译：提供一种用于制造用于磁电装置的包层导体（42）的方法。该方法包括提供衬底（10）并形成覆盖衬底（10）的导电阻挡层（12）。形成在导电阻挡层（12）上方的电介质层（16），并且在电介质层（16）的一部分内形成导电线（20）。去除电介质层（16），并且形成覆盖导线（20）的集流器（30）。

5. 发明授权

US06885074B2 Cladded conductor for use in a magnetoelectronics device and method for fabricating the same 有权
标题翻译：用于磁电子器件的包层导体及其制造方法
公开(公告)号：US06885074B2
公开(公告)日：2005-04-26
申请号：US10306250
申请日：2002-11-27
申请人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
发明人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
IPC分类号： G11C11/15 , H01L21/02 , H01L27/22 , H01L43/12 , H01L29/82 , H01L27/14
CPC分类号： H01L27/222 , G11C11/15 , H01L28/10 , H01L43/12
摘要： A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
摘要翻译：提供一种用于制造用于磁电装置的包层导体（42）的方法。该方法包括提供衬底（10）并形成覆盖衬底（10）的导电阻挡层（12）。形成在导电阻挡层（12）上方的电介质层（16），并且在电介质层（16）的一部分内形成导电线（20）。去除电介质层（16），并且形成覆盖导线（20）的集流器（30）。

6. 发明授权

US4974050A High voltage semiconductor device and method 失效
标题翻译：高压半导体器件及方法
公开(公告)号：US4974050A
公开(公告)日：1990-11-27
申请号：US358215
申请日：1989-05-30
申请人： Earl D. Fuchs
发明人： Earl D. Fuchs
IPC分类号： H01L29/06 , H01L29/868
CPC分类号： H01L29/0661 , H01L29/868
摘要： An improved method and structure for high voltage semiconductor devices capable of blocking voltages of the order of 1000 volts and greater is described. In a preferred embodiment, a blanket P layer is formed in an N.sup.- epi-layer on an N.sup.+ substrate. An annular groove is etched through the blanket P layer into the N.sup.- epi-layer. The bottom of the groove is doped N.sup.+ using the same mask as for the first groove etch. A second groove is formed inside of and partly overlapping the first groove and extending to a greater depth than the first groove, but not through the epi-layer. The second groove is fileld with passivating material, metal electrodes are applied to the P.sup.+ region and the N.sup.+ substrate, and the devices separated at the N.sup.+ region lying outside the second groove in the bottom of the first groove. Excellent high voltage blocking characteristics are obtained with the same or fewer process steps and better yield.
摘要翻译：描述了能够阻挡1000伏或更高数量级的电压的高电压半导体器件的改进的方法和结构。在优选实施例中，在N +衬底上的N外延层中形成覆盖层P层。通过橡皮布P层将环形槽蚀刻到N外延层中。使用与第一凹槽蚀刻相同的掩模，凹槽的底部掺杂N +。第二凹槽形成在第一凹槽的内部并且部分地与第一凹槽重叠并且延伸到比第一凹槽更大的深度，但不通过外延层。第二凹槽为钝化材料，金属电极施加到P +区域和N +衬底，并且器件在位于第一凹槽底部的第二沟槽外侧的N +区域分离。通过相同或更少的工艺步骤和更好的产率获得优异的高电压阻塞特性。

7. 发明申请

US20070290298A1 Semiconductor filter structure and method of manufacture 有权
标题翻译：半导体滤波器结构及其制造方法
公开(公告)号：US20070290298A1
公开(公告)日：2007-12-20
申请号：US11454387
申请日：2006-06-16
申请人： Sudhama Shastri , Ryan Hurley , Yenting Wen , Emily M. Linehan , Mark A. Thomas , Earl D. Fuchs
发明人： Sudhama Shastri , Ryan Hurley , Yenting Wen , Emily M. Linehan , Mark A. Thomas , Earl D. Fuchs
IPC分类号： H01L29/00
CPC分类号： H03H7/0107 , H01F17/0006 , H01F27/40 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H03H7/1766 , H01L2924/00
摘要： In one embodiment, a split well region of one conductivity type is formed in semiconductor substrate of an opposite conductivity type. The split well region forms one plate of a floating capacitor and an electrode of a transient voltage suppression device.
摘要翻译：在一个实施例中，一种导电类型的分裂阱区形成在相反导电类型的半导体衬底中。分裂阱区域形成浮动电容器的一个板和瞬态电压抑制装置的电极。

8. 发明授权

US08222115B2 Method of forming a high capacitance diode 有权
标题翻译：形成高容量二极管的方法
公开(公告)号：US08222115B2
公开(公告)日：2012-07-17
申请号：US13398356
申请日：2012-02-16
申请人： David D. Marreiro , Sudhama C. Shastri , Gordon M. Grivna , Earl D. Fuchs
发明人： David D. Marreiro , Sudhama C. Shastri , Gordon M. Grivna , Earl D. Fuchs
IPC分类号： H01L21/20
CPC分类号： H01L27/0814 , H01L29/8618 , H01L29/93 , Y10S438/963 , Y10S438/983
摘要： In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.
摘要翻译：在一个实施例中，高掺杂半导体沟道形成在相反导电类型的半导体区域中以增加器件的电容。

9. 发明申请

US20100072573A1 METHOD OF FORMING A HIGH CAPACITANCE DIODE AND STRUCTURE THEREFOR 有权
标题翻译：形成高电容二极管及其结构的方法
公开(公告)号：US20100072573A1
公开(公告)日：2010-03-25
申请号：US12630670
申请日：2009-12-03
申请人： David D. Marreiro , Sudhama C. Shastri , Gordon M. Grivna , Earl D. Fuchs
发明人： David D. Marreiro , Sudhama C. Shastri , Gordon M. Grivna , Earl D. Fuchs
IPC分类号： H01L29/861 , H01L21/02
CPC分类号： H01L27/0814 , H01L29/8618 , H01L29/93 , Y10S438/963 , Y10S438/983
摘要： In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.
摘要翻译：在一个实施例中，高掺杂半导体沟道形成在相反导电类型的半导体区域中以增加器件的电容。

10. 发明授权

US5286660A Method for doping a semiconductor wafer having a diffusivity enhancement region 失效
标题翻译：掺杂具有扩散增强区域的半导体晶片的方法
公开(公告)号：US5286660A
公开(公告)日：1994-02-15
申请号：US996747
申请日：1992-12-24
申请人： Herng-Der Chiou , Gary G. Ehlenberger , Earl D. Fuchs
发明人： Herng-Der Chiou , Gary G. Ehlenberger , Earl D. Fuchs
IPC分类号： H01L21/225 , H01L21/265 , H01L21/329 , H01L21/331
CPC分类号： H01L29/66106 , H01L21/2252 , H01L21/26506 , H01L29/66166 , H01L29/66272
摘要： A diffusivity and a solubility of dopant atoms are increased within a semiconductor wafer (30). A portion (36) of the semiconductor wafer (30) is disrupted by a technique of ion implantation thereby forming a defect layer (36). A predeposition layer (37) is formed by placing the semiconductor wafer (30) in a predeposition furnace. The defect layer (36) has a large number of point defects in a semiconductor crystal lattice which accept dopant atoms in excess of their solid solubility limit. The point defects increase the diffusivity and solubility of the dopant atoms thereby increasing a junction depth and surface concentration in subsequent high temperature diffusion steps.
摘要翻译：掺杂剂原子的扩散性和溶解度在半导体晶片（30）内增加。半导体晶片（30）的一部分（36）通过离子注入技术被破坏，从而形成缺陷层（36）。通过将半导体晶片（30）放置在预沉积炉中来形成预沉积层（37）。缺陷层（36）在接受掺杂剂原子超过其固溶度极限的半导体晶格中具有大量的点缺陷。点缺陷增加掺杂剂原子的扩散性和溶解度，从而增加随后的高温扩散步骤中的结深度和表面浓度。

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