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1. 发明授权

US09448846B2 Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines 有权
标题翻译：用于将作业调度到多个硬件加速引擎的动态配置的硬件队列
公开(公告)号：US09448846B2
公开(公告)日：2016-09-20
申请号：US13323914
申请日：2011-12-13
申请人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, Jr. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
发明人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, Jr. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
IPC分类号： G06F9/46 , G06F9/50 , G06F9/48
CPC分类号： G06F9/5038 , G06F9/4843 , G06F9/5027 , G06F2209/5021
摘要： A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.
摘要翻译：一种具有多个处理资源的计算机系统，包括用于向多个硬件加速器调度和调度处理作业的子系统，所述子系统还包括作业请求器，用于请求具有有限和变化的延迟的作业以在硬件上执行加速器队列控制器，用于管理针对多个硬件加速器的处理作业请求; 以及用于将作业分派到所述多个硬件加速引擎的多个硬件队列，每个队列具有专用的队列入口头部，动态共享具有可配置队列深度限制的队列条目池，以及用于移除所有队列中的一个或多个作业的装置。

2. 发明申请

US20130152099A1 DYNAMICALLY CONFIGURABLE HARDWARE QUEUES FOR DISPATCHING JOBS TO A PLURALITY OF HARDWARE ACCELERATION ENGINES 有权
公开(公告)号：US20130152099A1
公开(公告)日：2013-06-13
申请号：US13323914
申请日：2011-12-13
申请人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, JR. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
发明人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, JR. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
IPC分类号： G06F9/50
CPC分类号： G06F9/5038 , G06F9/4843 , G06F9/5027 , G06F2209/5021
摘要： A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.

3. 发明授权

US08230117B2 Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline 有权
标题翻译：在使用命令管道的一致性管理处理器系统中对写后排序进行排序的技术
公开(公告)号：US08230117B2
公开(公告)日：2012-07-24
申请号：US12420889
申请日：2009-04-09
申请人： George William Daly, Jr. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： George William Daly, Jr. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
IPC分类号： G06F3/00
CPC分类号： G06F13/4022
摘要： A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.
摘要翻译：用于在总线上维持输入/输出（I / O）命令排序的技术包括将信道标识符分配给I / O流的I / O命令。在这种情况下，通道标识符表示属于I / O流的I / O命令。命令位置指示符分配给每个I / O命令。命令位置指示器提供I / O命令中的哪一个是I / O流中的起始命令以及I / O命令中的哪一个在I / O流中继续命令的指示。 I / O命令以所需的完成顺序发出。当第一个I / O命令未成功完成时，I / O流中的I / O命令将从未成功完成的第一个I / O命令开始在总线上重新发出。

4. 发明申请

US20100262720A1 TECHNIQUES FOR WRITE-AFTER-WRITE ORDERING IN A COHERENCY MANAGED PROCESSOR SYSTEM THAT EMPLOYS A COMMAND PIPELINE 有权
标题翻译：在使用命令管道的协调管理处理器系统中进行写后写入的技术
公开(公告)号：US20100262720A1
公开(公告)日：2010-10-14
申请号：US12420889
申请日：2009-04-09
申请人： George William Daly, JR. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： George William Daly, JR. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
IPC分类号： G06F3/00
CPC分类号： G06F13/4022
摘要： A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.
摘要翻译：用于在总线上维持输入/输出（I / O）命令排序的技术包括将信道标识符分配给I / O流的I / O命令。在这种情况下，通道标识符表示属于I / O流的I / O命令。命令位置指示符分配给每个I / O命令。命令位置指示器提供I / O命令中的哪一个是I / O流中的起始命令以及I / O命令中的哪一个在I / O流中继续命令的指示。 I / O命令以所需的完成顺序发出。当第一个I / O命令未成功完成时，I / O流中的I / O命令将从未成功完成的第一个I / O命令开始在总线上重新发出。

5. 发明授权

US06769033B1 Network processor processing complex and methods 失效
标题翻译：网络处理器处理复杂和方法
公开(公告)号：US06769033B1
公开(公告)日：2004-07-27
申请号：US09384691
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Piyush Chunilal Patel , Mark Anthony Rinaldi , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Piyush Chunilal Patel , Mark Anthony Rinaldi , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F900
CPC分类号： H04L49/602 , G06F15/80 , H04L49/351
摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex with a suite of peripherals, all formed on a common semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.
摘要翻译：可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过嵌入式处理器复合体与一组外围设备的协作来增强数据流处理和灵活性，这些外围设备都形成在公共半导体衬底上。接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成于半导体衬底上的指令存储器中的指令的控制下操作，同时由存储器外围设备和与外部存储器元件的接口提供过渡数据流部分的存储。

6. 发明授权

US06829697B1 Multiple logical interfaces to a shared coprocessor resource 失效
标题翻译：到共享协处理器资源的多个逻辑接口
公开(公告)号：US06829697B1
公开(公告)日：2004-12-07
申请号：US09656582
申请日：2000-09-06
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
IPC分类号： G06F1500
CPC分类号： G06F15/7864
摘要： An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.
摘要翻译：嵌入式处理器复合体包含多个协议处理器单元（PPU）。每个单元包括至少一个，优选两个独立运行的核心语言处理器（CLP）。每个CLP支持双线程线程，其通过逻辑协处理器执行或数据接口与多个为每个PPU服务的专用协处理器进行交互。操作指令使PPU能够识别长时间和短的延迟事件，并根据此标识控制和转移线程执行的优先级。指令还可以在某些指定事件的发生或不发生时使特定协处理器操作的条件执行。

7. 发明授权

US07440417B2 Method and system for frame and protocol classification 失效
标题翻译：框架和协议分类的方法和系统
公开(公告)号：US07440417B2
公开(公告)日：2008-10-21
申请号：US10870730
申请日：2004-06-17
申请人： Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel , Jean Louis Calvignac , Gordon Taylor Davis
发明人： Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel , Jean Louis Calvignac , Gordon Taylor Davis
IPC分类号： H04L12/28
CPC分类号： H04L29/06 , H04L69/18 , H04L69/22
摘要： A system and method of protocol and frame classification in a system for data processing is disclosed, including, analyzing a portion of the, packet or frame according to predetermined tests, and storing characteristics of the packet for use in subsequent processing of the frame. The characteristics are preferably obtained with hardware, which does so quickly and in a uniform time period. The stored characteristics of the packet are then used by the network processing complexes in further processing of the frame. The processor is preconditioned with a starting instruction address or cede entry point and the location of the beginning of the layer 3 header as well as flags for the type of frame.
摘要翻译：公开了一种用于数据处理的系统中的协议和帧分类的系统和方法，包括：根据预定的测试分析一部分数据包或帧，以及存储该数据包的特性以用于帧的后续处理。这些特征优选地通过硬件获得，硬件在快速且均匀的时间周期内这样做。然后，分组的存储特性由网络处理复合体用于帧的进一步处理。处理器使用开始指令地址或者入门点进行预处理，并且第3层头的开始位置以及帧类型的标志。

8. 发明授权

US06775284B1 Method and system for frame and protocol classification 失效
标题翻译：框架和协议分类的方法和系统
公开(公告)号：US06775284B1
公开(公告)日：2004-08-10
申请号：US09479027
申请日：2000-01-07
申请人： Jean Louis Calvignac , Gordon Taylor Davis , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel
发明人： Jean Louis Calvignac , Gordon Taylor Davis , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel
IPC分类号： H04L1256
CPC分类号： H04L29/06 , H04L69/18 , H04L69/22
摘要： A system and method of protocol and frame classification in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the packet or frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit, such as the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address and flags indicating whether the frame uses a virtual local area network, preferably using hardware to quickly and in a uniform time period. The stored key characteristics of the packet are then used by the network processing complexes in its further processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additionally, additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions.
摘要翻译：用于数据处理（例如，切换或路由数据分组或帧）的系统中的协议和帧分类的系统和方法。本发明包括根据预定的测试来分析分组或帧的一部分，然后存储该分组的关键特征以用于该帧的后续处理。帧（或输入信息单元，例如帧中使用的层3协议的类型，第2层封装技术，起始指令地址和指示帧是否使用虚拟局域网的标志）的关键特性，优选地使用硬件在快速和统一的时间段内，存储的密钥特性随后由网络处理复合体在帧的进一步处理中被使用，处理器使用起始指令地址和开始指令的位置进行预处理第3层标题以及帧类型的标志，即处理器使用指令地址或代码入口点，根据帧类型对正确位置的帧开始处理，另外附加指令地址可以在分支上顺序堆叠和使用，以避免额外的测试和分支指令。

9. 发明授权

US08006244B2 Controller for multiple instruction thread processors 失效
标题翻译：多指令线程处理器的控制器
公开(公告)号：US08006244B2
公开(公告)日：2011-08-23
申请号：US10915983
申请日：2004-08-11
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
IPC分类号： G06F9/46
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译：机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。

10. 发明申请

US20080244130A1 FLOW LOOKAHEAD IN AN ORDERED SEMAPHORE MANAGEMENT SUBSYSTEM 失效
标题翻译：在订购的SEMAPHORE管理子系统中流动预览
公开(公告)号：US20080244130A1
公开(公告)日：2008-10-02
申请号：US12137818
申请日：2008-06-12
申请人： Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich , Wesley Erich Queen , Michael Steven Siegel
发明人： Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich , Wesley Erich Queen , Michael Steven Siegel
IPC分类号： G06F13/16
CPC分类号： G06F9/52
摘要： In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.
摘要翻译：在有序信号量管理系统中，待处理状态允许线程不竞争锁定的信号量绕过一个或多个线程等待相同的锁定信号量。挂起级别的数量决定了可绕过同一锁定信号量的连续线程的数量。当提供多个级别时，挂起的级别按排队顺序排列优先级。

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