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1. 发明授权

US06467053B1 Captured synchronous DRAM fails in a working environment 有权
标题翻译：捕获的同步DRAM在工作环境中失败
公开(公告)号：US06467053B1
公开(公告)日：2002-10-15
申请号：US09340804
申请日：1999-06-28
申请人： Brian J. Connolly , Steven A. Grundon , Bruce G. Hazelzet , Mark W. Kellogg , James R. Mallabar
发明人： Brian J. Connolly , Steven A. Grundon , Bruce G. Hazelzet , Mark W. Kellogg , James R. Mallabar
IPC分类号： G06F11277
CPC分类号： G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： A Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. The test assembly may be split into two segments: a diagnostic card and an adapter card to limit mechanical load on the system socket as well as permit varying form factors. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM products. The test assembly permits good and questionable synchronous modules to be compared using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments and may be otherwise difficult or impossible to replicate. The test assembly re-drives the system clocks with a phase lock loop (PLL) buffer to a memory module socket on the test assembly to permit timing adjustments to minimize the degradation to the system's memory bus timings due to the additional wire length and loading. The test assembly is programmable to adjust to varying bus timings such as: CAS (column address strobe) Latencies and Burst Length variations. It is designed with Field Programmable Gate Arrays (FPGAs) to allow for changes internally without modifying the test assembly.
摘要翻译：同步DRAM存储器测试组件，其将具有同步总线的普通PC或工作站转换为存储器测试器。测试组件可以分为两个部分：诊断卡和适配卡，以限制系统插座上的机械负载以及允许变化的外形尺寸。该测试组件架构支持66 MHz及以上的内存总线速度，并为逻辑分析仪提供方便的访问。测试组件支持注册和非缓冲同步DRAM产品。测试组件允许使用外部逻辑分析仪比较好的和有问题的同步模块。它允许解决在系统环境中唯一发生的系统内故障，并且可能难以或不可能复制。测试组件使用锁相环（PLL）缓冲区将系统时钟重新驱动到测试组件上的存储器模块插槽，以允许定时调整，以最大限度地减少系统的存储器总线时序由于额外的电线长度和负载而的劣化。测试组件可编程为适应变化的总线时序，例如：CAS（列地址选通）延迟和突发长度变化。它设计有现场可编程门阵列（FPGA），可在内部进行更改，无需修改测试组件。

2. 发明授权

US5802395A High density memory modules with improved data bus performance 失效
标题翻译：具有改进数据总线性能的高密度存储器模块
公开(公告)号：US5802395A
公开(公告)日：1998-09-01
申请号：US676609
申请日：1996-07-08
申请人： Brian J. Connolly , Mark W. Kellogg , Bruce G. Hazelzet
发明人： Brian J. Connolly , Mark W. Kellogg , Bruce G. Hazelzet
IPC分类号： G11C5/00 , G06F13/16 , G06F13/40 , G11C11/401 , H01L27/10 , G06F12/06 , G06F13/10 , G06F13/38
CPC分类号： G06F13/4068
摘要： Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. There are two parts to the solution of reducing data line capacitance to an acceptable system limit. The first part involves designing a memory module with in-line bus switches. The bus switches are placed between the module tabs (system) and random access memory devices and are either in a high impedance (off) or active state. When in the high impedance state, the effective loading of the module is that of the bit switch device. The second part of the solution is to embed logic into an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches. The bus switches become active on the falling edge of the system's RAS select line and stay active until the latter of the system's RAS or column address strobe (CAS) select lines going inactive, thereby supporting both Fast Page Mode (FPM) and Extended Data Output (EDO) operation. The circuit performs this task by decoding the system's RAS and CAS select lines and driving a signal to enable the bus switches.
摘要翻译：在具有多个DRAM的高密度模块上的数据线负载被最小化，从而可以增加其他有限密度的系统的最大存储器密度，而不会由于数据线容性负载而导致随后的性能下降。将数据线电容降低到可接受的系统限制的解决方案有两个部分。第一部分涉及设计具有在线总线开关的存储器模块。总线开关放置在模块卡舌（系统）和随机存取存储器件之间，并处于高阻抗（关闭）或激活状态。当处于高阻抗状态时，模块的有效负载是位开关器件的有效负载。解决方案的第二部分是将逻辑嵌入到专用集成电路（ASIC）中，该集成电路监控总线活动并控制总线交换机的激活。总线开关在系统的RAS选择线的下降沿变为有效，并保持有效，直到系统的RAS或列地址选通（CAS）选择线路不活动为止，从而支持快速页面模式（FPM）和扩展数据输出（EDO）操作。该电路通过解码系统的RAS和CAS选择线并驱动信号以启用总线开关来执行此任务。

3. 发明授权

US6070217A High density memory module with in-line bus switches being enabled in response to read/write selection state of connected RAM banks to improve data bus performance 失效
标题翻译：具有串行总线开关的高密度存储器模块响应于连接的RAM组的读/写选择状态而被使能，以提高数据总线性能
公开(公告)号：US6070217A
公开(公告)日：2000-05-30
申请号：US76265
申请日：1998-05-12
申请人： Brian J. Connolly , Bruce G. Hazelzet , Mark W. Kellogg
发明人： Brian J. Connolly , Bruce G. Hazelzet , Mark W. Kellogg
IPC分类号： G11C5/00 , G06F13/16 , G06F13/40 , G11C11/401 , H01L27/10 , G06F13/00 , G06F12/00 , G06F12/06
CPC分类号： G06F13/4068
摘要： Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. First the single or dual in-line memory module (SIMM or DIMM) includes in-line bus switches. The bus switches are between the SIMM or DIMM module tabs (system) and random access memory devices (RAM) and are either in a high impedance (off) or active state depending on the READ/WRITE state of the RAM. When in the high impedance state, the effective loading of the module is that of the bit switch device. The logic for determining the READ/WRITE state may be embedded in an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches, be provided by a memory controller or, generated by the RAM itself. The bus switches are active when the RAM is performing a read or a write and inactive otherwise. The RAM is Fast Page Mode (FPM) and Extended Data Output (EDO) or Synchronous DRAM (SDRAM).
摘要翻译：在具有多个DRAM的高密度模块上的数据线负载被最小化，从而可以增加其他有限密度的系统的最大存储器密度，而不会由于数据线容性负载而导致随后的性能下降。首先，单列或双列直插式内存模块（SIMM或DIMM）包括在线总线开关。总线开关位于SIMM或DIMM模块选项卡（系统）和随机存取存储设备（RAM）之间，并且根据RAM的读/写状态，处于高阻抗（关闭）或活动状态。当处于高阻态时，模块的有效负载是位开关器件的有效负载。用于确定读/写状态的逻辑可以被嵌入到专用集成电路（ASIC）中，该专用集成电路监视总线活动并控制总线开关的激活，由存储器控制器提供或由RAM本身产生。当RAM执行读或写操作时，总线开关处于活动状态。 RAM是快速页面模式（FPM）和扩展数据输出（EDO）或同步DRAM（SDRAM）。

4. 发明授权

US06349390B1 On-board scrubbing of soft errors memory module 有权
标题翻译：车载擦洗软错误内存模块
公开(公告)号：US06349390B1
公开(公告)日：2002-02-19
申请号：US09224990
申请日：1999-01-04
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg
IPC分类号： G06F1110
CPC分类号： G06F11/106
摘要： A memory module for attachment to a computer system having a memory bus and a method of using the memory module for error correction by scrubbing soft errors on-board the module is provided. The module includes a printed circuit card with memory storage chips on the card to store data bits and associated ECC check bits. Tabs are provided on the circuit card to couple the card to the memory bus of the computer system. Logic circuitry selectively operatively connects and disconnects the memory chip and the memory bus. A signal processor is connected in circuit relationship with the memory chips. The logic circuitry selectively permits the signal processor to read the stored data bits and associated check bits from the memory chips, recalculate the check bits from the read stored data bits, compare the recalculated check bits with the stored check bits, correct all at least one bit errors in the store data bits and stored associated check bits and re-store the correct data bits and associated check bits in the memory chips. When the memory chips and the memory bus are disconnected, single bit soft errors occurring during storage of the data bits and check bits are corrected periodically before the data is read from the memory chips to the data bus on a read operation.
摘要翻译：提供了一种用于附接到具有存储器总线的计算机系统的存储器模块，以及通过擦除模块上的软错误来使用存储器模块进行纠错的方法。该模块包括在卡上具有存储器存储芯片的印刷电路卡，以存储数据位和相关联的ECC校验位。在电路卡上提供标签以将该卡耦合到计算机系统的存储器总线。逻辑电路选择性地操作地连接和断开存储器芯片和存储器总线。信号处理器与存储器芯片以电路关系连接。逻辑电路选择性地允许信号处理器从存储器芯片读取存储的数据位和相关的校验位，从读取的存储的数据位重新计算校验位，将重新计算的校验位与存储的校验位进行比较，校正所有至少一个存储数据位和存储的相关检查位中的位错误并且将存储器芯片中的正确数据位和相关联的校验位重新存储。当存储器芯片和存储器总线断开时，在存储数据位和校验位期间发生的单位软错误在数据从读存储器芯片读取到数据总线之前被周期性地校正。

5. 发明授权

US06233639B1 Memory card utilizing two wire bus 失效
标题翻译：存储卡采用两条总线
公开(公告)号：US06233639B1
公开(公告)日：2001-05-15
申请号：US09225524
申请日：1999-01-04
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Clarence R. Ogilvie , Paul C. Stabler
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Clarence R. Ogilvie , Paul C. Stabler
IPC分类号： G06F1300
CPC分类号： G11C5/066
摘要： A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data. This serial information is received by the system memory controller which packets it, and, upon completion, outputs the information rapidly on a parallel bus, e.g. a PCI bus to the device which needs the information.
摘要翻译：在具有DSP和存储器总线控制器的存储卡上提供串行总线和通过系统存储器控制器与计算机系统上的设备的连接，以允许存储卡上的DSP访问系统设备而不使用系统内存总线串行总线是通过系统存储器控制器将设备连接到DSP的双线串行总线。如果多个存储卡存在于DSP或多于一个设备正在争取访问，则系统存储器控制器或仲裁每个存储卡或竞争设备的访问。在这种情况下，当串行总线想要访问特定设备时，串行总线将向系统存储器控制器发信号通知，并且系统存储器控制器将充当仲裁器以授予或不授予对请求访问的特定存储卡或设备的访问权限。如果访问被授予，总线存储器控制器在串行总线上输出所需的控制或命令字，然后输出地址和所需的数据。该串行信息由系统存储器控制器接收，该系统存储器控制器对其进行分组，并且在完成时，在并行总线上快速地输出信息，例如， PCI总线到需要信息的设备。

6. 发明授权

US07646649B2 Memory device with programmable receivers to improve performance 有权
标题翻译：具有可编程接收器的存储器件，以提高性能
公开(公告)号：US07646649B2
公开(公告)日：2010-01-12
申请号：US10707053
申请日：2003-11-18
申请人： Bruce G. Hazelzet , Mark W. Kellogg , Darcie J. Rankin
发明人： Bruce G. Hazelzet , Mark W. Kellogg , Darcie J. Rankin
IPC分类号： G11C11/00
CPC分类号： G06F13/4243 , G11C7/1078 , G11C7/109
摘要： A memory system having a plurality of DRAMs which are selectively provided non-inverted or inverted signals. The DRAMs have the ability to accept non-inverted or inverted address/command signals from a register that drives a plurality of signals simultaneously. The system includes DRAM receivers with programmable input polarity and a register with programmable output polarity.
摘要翻译：具有选择性地提供非反相或反相信号的多个DRAM的存储器系统。 DRAM具有从同时驱动多个信号的寄存器接受非反相或反相地址/命令信号的能力。该系统包括具有可编程输入极性的DRAM接收器和具有可编程输出极性的寄存器。

7. 发明授权

US06327664B1 Power management on a memory card having a signal processing element 失效
标题翻译：对具有信号处理元件的存储卡进行电源管理
公开(公告)号：US06327664B1
公开(公告)日：2001-12-04
申请号：US09302916
申请日：1999-04-30
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Christopher P. Miller
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Christopher P. Miller
IPC分类号： G06F132
CPC分类号： G06F1/3275 , G06F1/3203 , Y02D10/13 , Y02D10/14
摘要： An improved memory module and its use in a computer system is provided. The module includes a DSP first and second individually addressable banks of memory chips. The first bank is configured to function principally under the control of the signal processing element and the second bank is configured to function principally under the control of a system memory controller, although all the portions of each of the memory banks is addressable by both the signal processing element and the system memory controller. Both banks of memory chips can be placed in at least one higher power state and at least one lower power state by either the system memory controller or the DSP. The activity of each bank is sensed while in the higher power state, and the condition of each of the banks is sensed with respect to any activity during operation of the memory bank at the higher power state. The power state of each bank can be changed by either the signal processing element or the system memory controller responsive to preselected conditions of each bank. Each memory bank is returned to a predetermined known condition when changing from a lower power state to a higher power state. This is especially important when the memory bank assigned to the system controller is placed in another state by the DSP.
摘要翻译：提供了一种改进的存储器模块及其在计算机系统中的应用。该模块包括DSP第一和第二可单独寻址的存储器芯片组。第一组被配置为主要在信号处理元件的控制下起作用，并且第二存储体被配置为主要在系统存储器控制器的控制下起作用，尽管每个存储体的所有部分都可以由信号处理元件和系统存储器控制器。两个存储芯片组可以通过系统存储器控制器或DSP被置于至少一个较高功率状态和至少一个较低功率状态。在较高功率状态下感测每个存储体的活动，并且相对于在较高功率状态的存储体的操作期间的任何活动来感测每个存储体的状况。响应于每个银行的预选条件，可以通过信号处理元件或系统存储器控制器改变每个存储体的电源状态。当从较低功率状态改变到较高功率状态时，每个存储体返回到预定的已知状态。当分配给系统控制器的存储体被DSP置于另一状态时，这尤其重要。

8. 发明授权

US06385685B1 Memory card utilizing two wire bus 失效
公开(公告)号：US06385685B1
公开(公告)日：2002-05-07
申请号：US09833871
申请日：2001-04-12
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Clarence R. Ogilvie , Paul C. Stabler
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Clarence R. Ogilvie , Paul C. Stabler
IPC分类号： G06F1338
CPC分类号： G11C5/066
摘要： A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data. This serial information is received by the system memory controller which packets it, and, upon completion, outputs the information rapidly on a parallel bus, e.g. a PCI bus to the device which needs the information.

9. 发明授权

US5757712A Memory modules with voltage regulation and level translation 失效
标题翻译：具有电压调节和电平转换的内存模块
公开(公告)号：US5757712A
公开(公告)日：1998-05-26
申请号：US678867
申请日：1996-07-12
申请人： Johann W. Nagel , Mark W. Kellogg , Bruce G. Hazelzet
发明人： Johann W. Nagel , Mark W. Kellogg , Bruce G. Hazelzet
IPC分类号： G11C5/00 , G11C5/14 , G11C7/10 , H05K1/02
CPC分类号： H05K1/0256 , G11C5/147 , G11C7/1006 , H05K1/0262 , H05K2201/10166 , H05K2201/10196 , H05K2201/10689
摘要： Low voltage DRAMs are used on higher voltage memory modules in a way that requires no modification of the DRAMs. "Bus switch" technology and compact low voltage regulators are used at the module level. The low voltage regulator provides a lowered, regulated voltage to DRAMs. The bus switches are used at the inputs and outputs of the DRAMs and effectively protect the DRAM circuitry from voltage swings that could otherwise be damaging.
摘要翻译：低电压DRAM以不需要修改DRAM的方式用于高电压存储器模块。在模块级使用“总线开关”技术和紧凑型低压调节器。低电压调节器为DRAM提供降低的稳压电压。总线开关用于DRAM的输入和输出，并有效地保护DRAM电路免受可能会造成损害的电压摆幅。

10. 发明授权

US6118719A Self-initiated self-refresh mode for memory modules 失效
标题翻译：内存模块的自启动自刷新模式
公开(公告)号：US6118719A
公开(公告)日：2000-09-12
申请号：US81639
申请日：1998-05-20
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A method and apparatus for selectively causing each bank of a number of banks of DRAMs of a DRAM memory card to enter into the self-refresh mode without affecting the operation of any other bank. In the computer system incorporating the SIMM or DIMM type DRAM cards, each bank of memory on each card has a RAS signal specific to that specific bank. One or more CAS signals are supplied across all of the memory banks, on all cards. Thus, each memory bank is accessed separately for a read/write operation by the RAS becoming active before the CAS becomes active; and refresh takes place by the CAS signal becoming active before the RAS signal becomes active. The number of clock cycles or refresh cycles between active RAS signals to each memory bank are counted. If RAS does not become active for N clock or refresh cycles, a signal is provided within each respective memory bank and that memory bank will immediately, or preferably after M additional clock or refresh cycles enter self-refresh mode without affecting the operation of any other bank. At the same time, the memory controller counts cycles of RAS inactivity for each DRAM bank it controls. A signal is also provided to a register to require a double read/write on the next active read/write cycle to that bank, for reactivating that bank from the self-refresh mode when RAS signal specific to that bank becomes active while CAS is inactive.
摘要翻译：一种用于选择性地使DRAM存储卡的DRAM组的每一组进入自刷新模式而不影响任何其他存储体的操作的方法和装置。在包含SIMM或DIMM型DRAM卡的计算机系统中，每张卡上的每一组存储器具有特定于该特定存储体的RAS信号。所有卡上的所有存储体都提供一个或多个CAS信号。因此，在CAS变为活动状态之前，RAS变为活动状态的每个存储体被单独访问用于读/写操作; 并且在RAS信号变为有效之前，CAS信号变为有效，刷新发生。计数到每个存储体的有效RAS信号之间的时钟周期数或刷新周期数。如果RAS对于N个时钟或刷新周期没有变为有效，则在每个相应的存储体内提供一个信号，并且该存储体将立即或优选地在M个附加时钟或刷新周期进入自刷新模式之后不影响任何其它的操作银行。同时，存储器控制器控制其控制的每个DRAM组的RAS不活动的周期。还向寄存器提供一个信号，要求在该存储体的下次有效读/写周期上进行双重读/写操作，当CAS不活动时，RAS特定于该存储体的信号变为活动状态时，从自刷新模式重新激活该存储体。

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