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1. 发明授权

US07761697B1 Processing an indirect branch instruction in a SIMD architecture 有权
标题翻译：在SIMD架构中处理间接分支指令
公开(公告)号：US07761697B1
公开(公告)日：2010-07-20
申请号：US11557082
申请日：2006-11-06
申请人： Brett W. Coon , John Erik Lindholm , Peter C. Mills , John R. Nickolls
发明人： Brett W. Coon , John Erik Lindholm , Peter C. Mills , John R. Nickolls
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/30072 , G06F9/3009 , G06F9/30185 , G06F9/322 , G06F9/3851 , G06F9/3887
摘要： One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetching a program instruction, determining that the program instruction is an indirect branch instruction, and processing the indirect branch instruction as a sequence of two-way branches to execute an indirect branch instruction with multiple branch addresses. Indirect branch instructions may be used to allow greater flexibility since the branch address or multiple branch addresses do not need to be determined at compile time.
摘要翻译：被配置为管理线程组中的发散线程的计算系统的一个实施例包括配置成存储至少一个令牌和多线程处理单元的堆栈。多线程处理单元被配置为执行以下步骤：获取程序指令，确定程序指令是间接分支指令，以及将间接分支指令处理为双向分支序列，以执行具有多个分支的间接分支指令地址可以使用间接分支指令来允许更大的灵活性，因为在编译时不需要确定分支地址或多个分支地址。

2. 发明申请

US20090240931A1 Indirect Function Call Instructions in a Synchronous Parallel Thread Processor 有权
标题翻译：同步并行线程处理器中的间接函数调用指令
公开(公告)号：US20090240931A1
公开(公告)日：2009-09-24
申请号：US12054255
申请日：2008-03-24
申请人： Brett W. Coon , John R. Nickolls , Lars Nyland , Peter C. Mills , John Erik Lindholm
发明人： Brett W. Coon , John R. Nickolls , Lars Nyland , Peter C. Mills , John Erik Lindholm
IPC分类号： G06F9/38
CPC分类号： G06F9/38 , G06F9/30054 , G06F9/30101 , G06F9/3851 , G06F9/3885
摘要： An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.
摘要翻译：间接分支指令将地址寄存器作为参数，以便为单指令多线程（SIMT）处理器架构提供间接函数调用能力。间接分支指令用于实现间接函数调用，虚函数调用和switch语句，以提高处理性能，与使用连续的测试和分支链相比。

3. 发明授权

US08312254B2 Indirect function call instructions in a synchronous parallel thread processor 有权
标题翻译：同步并行线程处理器中的间接函数调用指令
公开(公告)号：US08312254B2
公开(公告)日：2012-11-13
申请号：US12054255
申请日：2008-03-24
申请人： Brett W. Coon , John R. Nickolls , Lars Nyland , Peter C. Mills , John Erik Lindholm
发明人： Brett W. Coon , John R. Nickolls , Lars Nyland , Peter C. Mills , John Erik Lindholm
IPC分类号： G06F9/00
CPC分类号： G06F9/38 , G06F9/30054 , G06F9/30101 , G06F9/3851 , G06F9/3885
摘要： An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.
摘要翻译：间接分支指令将地址寄存器作为参数，以便为单指令多线程（SIMT）处理器架构提供间接函数调用能力。间接分支指令用于实现间接函数调用，虚函数调用和switch语句，以提高处理性能，与使用连续的测试和分支链相比。

4. 发明授权

US07877585B1 Structured programming control flow in a SIMD architecture 有权
标题翻译： SIMD架构中的结构化编程控制流程
公开(公告)号：US07877585B1
公开(公告)日：2011-01-25
申请号：US11845429
申请日：2007-08-27
申请人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Svetoslav D. Tzvetkov
发明人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Svetoslav D. Tzvetkov
IPC分类号： G06F15/76 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/3885 , G06F9/3887
摘要： One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A parallel processing unit is configured to perform the steps of determining if one or more threads diverge during execution of a conditional control instruction. A disable mask allows for the use of conditional return and break instructions in a multithreaded SIMD architecture. Additional control instructions are used to set up thread processing target addresses for synchronization, breaks, and returns.
摘要翻译：被配置为管理SIMD线程组中的发散线程的计算系统的一个实施例包括被配置为存储用于处理控制指令的状态信息的堆栈。并行处理单元被配置为执行在执行条件控制指令期间确定一个或多个线程是否发散的步骤。禁用掩码允许在多线程SIMD架构中使用条件返回和中断指令。附加控制指令用于设置线程处理目标地址以进行同步，中断和返回。

5. 发明申请

US20120110586A1 THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR 有权
标题翻译：用于并行螺纹加工器的螺纹组合调度器
公开(公告)号：US20120110586A1
公开(公告)日：2012-05-03
申请号：US13247819
申请日：2011-09-28
申请人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette , Kathleen Elliott Nickolls
发明人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette , Kathleen Elliott Nickolls
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/483
摘要： A parallel thread processor executes thread groups belonging to multiple cooperative thread arrays (CTAs). At each cycle of the parallel thread processor, an instruction scheduler selects a thread group to be issued for execution during a subsequent cycle. The instruction scheduler selects a thread group to issue for execution by (i) identifying a pool of available thread groups, (ii) identifying a CTA that has the greatest seniority value, and (iii) selecting the thread group that has the greatest credit value from within the CTA with the greatest seniority value.
摘要翻译：并行线程处理器执行属于多个协作线程数组（CTA）的线程组。在并行线程处理器的每个周期，指令调度器在随后的周期中选择要发行的线程组以执行。指令调度器通过（i）识别可用线程组的池，（ii）识别具有最大资历值的CTA来选择要执行的线程组，以及（iii）选择具有最大信用值的线程组从具有最高资历价值的CTA内。

6. 发明授权

US07456835B2 Register based queuing for texture requests 有权
标题翻译：基于注册排队的纹理请求
公开(公告)号：US07456835B2
公开(公告)日：2008-11-25
申请号：US11339937
申请日：2006-01-25
申请人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
发明人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
IPC分类号： G06T11/40 , G06T15/00 , G06T1/00 , G09G5/00
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.
摘要翻译：图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。专用纹理请求缓冲区排队相对较小的纹理命令和参数。另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。纹理单元从纹理请求缓冲区中检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。

7. 发明授权

US07027062B2 Register based queuing for texture requests 有权
公开(公告)号：US07027062B2
公开(公告)日：2006-04-11
申请号：US10789735
申请日：2004-02-27
申请人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
发明人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
IPC分类号： G06T11/40
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

8. 发明授权

US07864185B1 Register based queuing for texture requests 有权
标题翻译：基于注册排队的纹理请求
公开(公告)号：US07864185B1
公开(公告)日：2011-01-04
申请号：US12256848
申请日：2008-10-23
申请人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
发明人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
IPC分类号： G06T11/40 , G06T15/00 , G06T15/20 , G06T1/00
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.
摘要翻译：图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。专用纹理请求缓冲区排队相对较小的纹理命令和参数。另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。纹理单元从纹理请求缓冲区中检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。

9. 发明授权

US07634621B1 Register file allocation 有权
标题翻译：注册文件分配
公开(公告)号：US07634621B1
公开(公告)日：2009-12-15
申请号：US11556677
申请日：2006-11-03
申请人： Brett W. Coon , John Erik Lindholm , Gary Tarolli , Svetoslav D. Tzvetkov , John R. Nickolls , Ming Y. Siu
发明人： Brett W. Coon , John Erik Lindholm , Gary Tarolli , Svetoslav D. Tzvetkov , John R. Nickolls , Ming Y. Siu
IPC分类号： G06F12/00
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F12/0223 , Y02D10/13
摘要： Circuits, methods, and apparatus that provide the die area and power savings of a single-ported memory with the performance advantages of a multiported memory. One example provides register allocation methods for storing data in a multiple-bank register file. In a thin register allocation method, data for a process is stored in a single bank. In this way, different processes use different banks to avoid conflicts. In a fat register allocation method, processes store data in each bank. In this way, if one process uses a large number of registers, those registers are spread among the banks, avoiding a situation where one bank is filled and other processes are forced to share a reduced number of banks. In a hybrid register allocation method, processes store data in more than one bank, but fewer than all the banks. Each of these methods may be combined in varying ways.
摘要翻译：提供具有多端口存储器性能优势的单端口存储器的管芯面积和功率节省的电路，方法和装置。一个示例提供用于将数据存储在多存储器寄存器文件中的寄存器分配方法。在一个薄的寄存器分配方法中，一个进程的数据被存储在一个单独的存储单元中。以这种方式，不同的流程使用不同的银行来避免冲突。在胖寄存器分配方法中，处理将数据存储在每个存储区中。这样一来，如果一个进程使用大量的寄存器，这些寄存器就会在银行之间传播，避免了一个银行被填满的情况，而其他进程被迫分担一个数量减少的银行。在混合寄存器分配方法中，处理将数据存储在多个银行中，但少于所有银行。这些方法中的每一种可以以不同的方式组合。

10. 发明授权

US07949855B1 Scheduler in multi-threaded processor prioritizing instructions passing qualification rule 有权
标题翻译：多线程处理器调度器优先级指令通过资格规则
公开(公告)号：US07949855B1
公开(公告)日：2011-05-24
申请号：US12110942
申请日：2008-04-28
申请人： Peter C. Mills , John Erik Lindholm , Brett W. Coon , Gary M. Tarolli , John Matthew Burgess
发明人： Peter C. Mills , John Erik Lindholm , Brett W. Coon , Gary M. Tarolli , John Matthew Burgess
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/3853 , G06F9/3867 , G06F9/3885
摘要： A processor buffers asynchronous threads. Instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one computation operation and at least one memory access operation. Instructions within each phase are qualified and prioritized. The instructions may be qualified based on the status of the execution unit needed to execute one or more of the current instructions. The instructions may also be qualified based on an age of each instruction, status of the execution units, a divergence potential, locality, thread diversity, and resource requirements. Qualified instructions may be prioritized based on execution units needed to execute instructions and the execution units in use. One or more of the prioritized instructions is issued per cycle to the plurality of execution units.
摘要翻译：处理器缓冲异步线程。由多个执行单元提供的需要操作的指令被划分为相位，每个阶段具有至少一个计算操作和至少一个存储器访问操作。每个阶段的说明是合格的，并且是优先考虑的。可以基于执行一个或多个当前指令所需的执行单元的状态来限制指令。指令也可以基于每个指令的年龄，执行单元的状态，发散电位，局部性，线程分集和资源需求来限定。可以根据执行指令所需的执行单元和正在使用的执行单元来优先确定合格的指令。每个周期向多个执行单元发出一个或多个优先指令。

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