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1. 发明授权

US07577212B2 Method and system for generating reference voltages for signal receivers 有权
标题翻译：用于产生信号接收机参考电压的方法和系统
公开(公告)号：US07577212B2
公开(公告)日：2009-08-18
申请号：US10930543
申请日：2004-08-30
申请人： Brent Keeth , Joo S. Choi , George E. Pax , Ronnie M. Harrison , David Ovard , Dragos Dimitriu , Troy A. Manning , Roy E. Greeff , Greg King , Brian Johnson
发明人： Brent Keeth , Joo S. Choi , George E. Pax , Ronnie M. Harrison , David Ovard , Dragos Dimitriu , Troy A. Manning , Roy E. Greeff , Greg King , Brian Johnson
IPC分类号： H03K9/00
CPC分类号： H04L25/062
摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.
摘要翻译：用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。在正常操作期间将该最终参考电压施加到接收器。

2. 发明授权

US07746959B2 Method and system for generating reference voltages for signal receivers 有权
标题翻译：用于产生信号接收机参考电压的方法和系统
公开(公告)号：US07746959B2
公开(公告)日：2010-06-29
申请号：US11433322
申请日：2006-05-11
申请人： Brent Keeth , Joo S. Choi , George E. Pax , Ronnie M. Harrison , David Ovard , Dragos Dimitriu , Troy A. Manning , Roy E. Greeff , Greg King , Brian Johnson
发明人： Brent Keeth , Joo S. Choi , George E. Pax , Ronnie M. Harrison , David Ovard , Dragos Dimitriu , Troy A. Manning , Roy E. Greeff , Greg King , Brian Johnson
IPC分类号： H04L25/06
CPC分类号： H04L25/062
摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.
摘要翻译：用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。在正常操作期间将该最终参考电压施加到接收器。

3. 发明授权

US07557601B2 Memory module and method having improved signal routing topology 失效
标题翻译：具有改进的信号路由拓扑的存储器模块和方法
公开(公告)号：US07557601B2
公开(公告)日：2009-07-07
申请号：US11973684
申请日：2007-10-09
申请人： George E. Pax , Roy E. Greeff
发明人： George E. Pax , Roy E. Greeff
IPC分类号： H03K19/003
CPC分类号： G11C5/04 , G11C5/025 , G11C5/063 , G11C11/409 , H05K1/025 , H05K1/181 , H05K2201/09254 , Y02P70/611
摘要： A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.
摘要翻译：注册的存储器模块包括通过形成对称树形拓扑的多条传输线耦合到寄存器的多个存储器件。树包括几个分支，每个分支包括仅在其端部耦合到另一个传输线或一个存储器件的两个传输线。分支被布置成几层次，分支中的传输线具有相同长度的相同层级。每个传输线优选地具有特性阻抗，其是与其耦合的任何一对下游传输线的特性阻抗的一半以提供阻抗匹配。专用传输线用于将附加的存储器件（其可能是或可能不是错误检查存储器件）耦合到寄存器。

4. 发明授权

US07746095B2 Memory module and method having improved signal routing topology 有权
标题翻译：具有改进的信号路由拓扑的存储器模块和方法
公开(公告)号：US07746095B2
公开(公告)日：2010-06-29
申请号：US12480589
申请日：2009-06-08
申请人： George E. Pax , Roy E. Greeff
发明人： George E. Pax , Roy E. Greeff
IPC分类号： H03K19/003
CPC分类号： G11C5/04 , G11C5/025 , G11C5/063 , G11C11/409 , H05K1/025 , H05K1/181 , H05K2201/09254 , Y02P70/611
摘要： A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.
摘要翻译：注册的存储器模块包括通过形成对称树形拓扑的多条传输线耦合到寄存器的多个存储器件。树包括几个分支，每个分支包括仅在其端部耦合到另一个传输线或一个存储器件的两个传输线。分支被布置成几层次，分支中的传输线具有相同长度的相同层级。每个传输线优选地具有特性阻抗，其是与其耦合的任何一对下游传输线的特性阻抗的一半以提供阻抗匹配。专用传输线用于将附加的存储器件（其可能是或可能不是错误检查存储器件）耦合到寄存器。

5. 发明授权

US07245145B2 Memory module and method having improved signal routing topology 有权
标题翻译：具有改进的信号路由拓扑的存储器模块和方法
公开(公告)号：US07245145B2
公开(公告)日：2007-07-17
申请号：US10460588
申请日：2003-06-11
申请人： George E. Pax , Roy E. Greeff
发明人： George E. Pax , Roy E. Greeff
IPC分类号： H03K19/003 , H03K19/0175 , H01L21/8242 , G06F15/00 , G11C5/00
CPC分类号： G11C5/04 , G11C5/025 , G11C5/063 , G11C11/409 , H05K1/025 , H05K1/181 , H05K2201/09254 , Y02P70/611
摘要： A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.
摘要翻译：注册的存储器模块包括通过形成对称树形拓扑的多条传输线耦合到寄存器的多个存储器件。树包括几个分支，每个分支包括仅在其端部耦合到另一个传输线或一个存储器件的两个传输线。分支被布置成几层次，分支中的传输线具有相同长度的相同层级。每个传输线优选地具有特性阻抗，其是与其耦合的任何一对下游传输线的特性阻抗的一半以提供阻抗匹配。专用传输线用于将附加的存储器件（其可能是或可能不是错误检查存储器件）耦合到寄存器。

6. 发明授权

US06937057B2 Memory module and method having improved signal routing topology 有权
公开(公告)号：US06937057B2
公开(公告)日：2005-08-30
申请号：US10460588
申请日：2003-06-11
申请人： George E. Pax , Roy E. Greeff
发明人： George E. Pax , Roy E. Greeff
摘要： A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

7. 发明申请

US20090243649A1 MEMORY MODULE AND METHOD HAVING IMPROVED SIGNAL ROUTING TOPOLOGY 有权
标题翻译：具有改进信号路由拓扑的记忆模块和方法
公开(公告)号：US20090243649A1
公开(公告)日：2009-10-01
申请号：US12480589
申请日：2009-06-08
申请人： George E. Pax , Roy E. Greeff
发明人： George E. Pax , Roy E. Greeff
IPC分类号： H03K19/003
CPC分类号： G11C5/04 , G11C5/025 , G11C5/063 , G11C11/409 , H05K1/025 , H05K1/181 , H05K2201/09254 , Y02P70/611
摘要： A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.
摘要翻译：注册的存储器模块包括通过形成对称树形拓扑的多条传输线耦合到寄存器的多个存储器件。树包括几个分支，每个分支包括仅在其端部耦合到另一个传输线或一个存储器件的两个传输线。分支被布置成几层次，分支中的传输线具有相同长度的相同层级。每个传输线优选地具有特性阻抗，其是与其耦合的任何一对下游传输线的特性阻抗的一半以提供阻抗匹配。专用传输线用于将附加的存储器件（其可能是或可能不是错误检查存储器件）耦合到寄存器。

8. 发明授权

US07242213B2 Memory module and method having improved signal routing topology 有权
公开(公告)号：US07242213B2
公开(公告)日：2007-07-10
申请号：US10932477
申请日：2004-09-01
申请人： George E. Pax , Roy E. Greeff
发明人： George E. Pax , Roy E. Greeff
IPC分类号： H03K19/03 , H01L21/8242 , H01L25/00 , G11C7/08
CPC分类号： G11C5/04 , G11C5/025 , G11C5/063 , G11C11/409 , H05K1/025 , H05K1/181 , H05K2201/09254 , Y02P70/611
摘要： A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

9. 发明授权

US07282947B2 Memory module and method having improved signal routing topology 失效
公开(公告)号：US07282947B2
公开(公告)日：2007-10-16
申请号：US11238900
申请日：2005-09-28
申请人： George E. Pax , Roy E. Greeff
发明人： George E. Pax , Roy E. Greeff
IPC分类号： H03K19/003
CPC分类号： G11C5/04 , G11C5/025 , G11C5/063 , G11C11/409 , H05K1/025 , H05K1/181 , H05K2201/09254 , Y02P70/611
摘要： A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

10. 发明授权

US5210509A Dual loop phase locked circuit with sweep generator and compensation for drift 失效
标题翻译：具有扫描发生器和漂移补偿的双回路锁相电路
公开(公告)号：US5210509A
公开(公告)日：1993-05-11
申请号：US891373
申请日：1992-05-29
申请人： Roy E. Greeff , Bruce H. Williams , Mark B. Falslev
发明人： Roy E. Greeff , Bruce H. Williams , Mark B. Falslev
IPC分类号： H03L7/12
CPC分类号： H03L7/12 , Y10S331/02
摘要： A dual loop phase locked circuit is disclosed in which a first loop includes a phase detector, a filter, and a VCO; as a second loop includes a sweep voltage generator, a compensation circuit, and the filter of the first loop. Due to the compensation circuit, the VCO accurately tracks a signal from the sweep voltage generator, even though the filter has an electrical parameter that drifts with time and/or age and/or component selection.
摘要翻译：公开了一种双回路锁相电路，其中第一环路包括相位检测器，滤波器和VCO; 作为第二回路包括扫频电压发生器，补偿电路和第一回路的滤波器。由于补偿电路，即使滤波器具有随时间和/或年龄和/或元件选择而漂移的电参数，VCO也可精确地跟踪来自扫描电压发生器的信号。

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