专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080177943A1 Method and system for using dynamic random access memory as cache memory 有权
标题翻译：使用动态随机存取存储器作为高速缓冲存储器的方法和系统
公开(公告)号：US20080177943A1
公开(公告)日：2008-07-24
申请号：US12069812
申请日：2008-02-12
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
摘要翻译：高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

2. 发明授权

US07917692B2 Method and system for using dynamic random access memory as cache memory 有权
标题翻译：使用动态随机存取存储器作为高速缓冲存储器的方法和系统
公开(公告)号：US07917692B2
公开(公告)日：2011-03-29
申请号：US12069812
申请日：2008-02-12
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
摘要翻译：高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

3. 发明授权

US06948027B2 Method and system for using dynamic random access memory as cache memory 失效
公开(公告)号：US06948027B2
公开(公告)日：2005-09-20
申请号：US10815877
申请日：2004-03-30
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
IPC分类号： G11C7/10 , G11C11/406 , G11C11/409 , G11C15/04 , G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

4. 发明授权

US07350018B2 Method and system for using dynamic random access memory as cache memory 有权
标题翻译：使用动态随机存取存储器作为高速缓冲存储器的方法和系统
公开(公告)号：US07350018B2
公开(公告)日：2008-03-25
申请号：US11595370
申请日：2006-11-08
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
IPC分类号： G06F12/16
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAMs are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
摘要翻译：高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且还包括2个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。在操作中，从DRAM的存储体中读取的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

5. 发明授权

US06862654B1 Method and system for using dynamic random access memory as cache memory 失效
标题翻译：使用动态随机存取存储器作为高速缓冲存储器的方法和系统
公开(公告)号：US06862654B1
公开(公告)日：2005-03-01
申请号：US09642546
申请日：2000-08-17
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
IPC分类号： G11C7/10 , G11C11/406 , G11C11/409 , G11C15/04 , G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
摘要翻译：高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且还包括2个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

6. 发明授权

US06445636B1 Method and system for hiding refreshes in a dynamic random access memory 有权
标题翻译：用于在动态随机存取存储器中隐藏刷新的方法和系统
公开(公告)号：US06445636B1
公开(公告)日：2002-09-03
申请号：US09641881
申请日：2000-08-17
申请人： Brent Keeth , Brian M. Shirley , Kevin J. Ryan , Charles H. Dennison
发明人： Brent Keeth , Brian M. Shirley , Kevin J. Ryan , Charles H. Dennison
IPC分类号： G11C700
CPC分类号： G11C11/40618 , G11C7/1042 , G11C11/406
摘要： A method and system for refreshing a dynamic random access memory (“DRAM”) includes a pair of memory arrays for each of a plurality of banks. The DRAM includes the usual addressing and data path circuitry, as well as a refresh controller that refreshes the arrays in a manner that hides refreshes sufficiently that the DRAM can be used in place of an SRAM as a cache memory. Since only one of the arrays in each bank is refreshed at a time, the refresh controller is able to allow data to be written to the array that is not being refreshed. The refresh controller then causes the write data to be temporarily stored so that it can be written to the array of the refresh of the array has been completed. If neither array is being refreshed, the data are written to both arrays. Data are read from the arrays by first checking to determine if any of the arrays is being refreshed. If so, data are read from the array that is not being refreshed.
摘要翻译：用于刷新动态随机存取存储器（“DRAM”）的方法和系统包括用于多个存储体中的每一个的一对存储器阵列。 DRAM包括通常的寻址和数据路径电路，以及刷新控制器，其以隐藏更充分的方式刷新阵列，使得DRAM可以用来代替SRAM作为高速缓冲存储器。由于每次刷新每个存储体中只有一个阵列，所以刷新控制器能够将数据写入未刷新的数组。然后，刷新控制器使得写入数据被临时存储，使得其可以被写入阵列的刷新的阵列已经完成。如果两个数组都不被刷新，数据将被写入两个数组。通过首先检查来确定数组是否被刷新，从数组中读取数据。如果是这样，数据从数组中读取，没有被刷新。

7. 发明授权

US07027349B2 Method for selecting memory device in response to bank selection signal 失效
标题翻译：响应存储体选择信号选择存储器件的方法
公开(公告)号：US07027349B2
公开(公告)日：2006-04-11
申请号：US10969177
申请日：2004-10-21
申请人： Kevin J. Ryan , Brent Keeth
发明人： Kevin J. Ryan , Brent Keeth
IPC分类号： G11C8/00
CPC分类号： G11C8/12
摘要： A method and apparatus is provided for selecting a memory device or a group of memory devices in a memory system using dedicated bank select signals in combination with encoded chip selection signals. A memory controller transmits bank select signals over bank select signal lines and encoded chip select signals on the command and address bus which are used to select an individual memory device or group of memory devices in a bank for an operation.
摘要翻译：提供了一种方法和装置，用于使用专门的存储体选择信号与编码的芯片选择信号结合来选择存储器系统中的存储器件或一组存储器件。存储器控制器通过存储体选择信号线发送存储体选择信号，并在命令和地址总线上传送编码的芯片选择信号，这些信号用于选择用于操作的存储体中的各个存储器件或存储器组组。

8. 发明授权

US06658523B2 System latency levelization for read data 有权
公开(公告)号：US06658523B2
公开(公告)日：2003-12-02
申请号：US09804221
申请日：2001-03-13
申请人： Jeffery W. Janzen , Brent Keeth , Kevin J. Ryan , Troy A. Manning , Brian Johnson
发明人： Jeffery W. Janzen , Brent Keeth , Kevin J. Ryan , Troy A. Manning , Brian Johnson
IPC分类号： G06F1200
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

9. 发明授权

US06535450B1 Method for selecting one or a bank of memory devices 有权
公开(公告)号：US06535450B1
公开(公告)日：2003-03-18
申请号：US09640759
申请日：2000-08-18
申请人： Kevin J. Ryan , Brent Keeth
发明人： Kevin J. Ryan , Brent Keeth
IPC分类号： G11C800
CPC分类号： G11C8/12
摘要： A method and apparatus is provided for selecting a memory device or a group of memory devices in a memory system using dedicated bank select signals in combination with encoded chip selection signals. A memory controller transmits bank select signals over bank select signal lines and encoded chip select signals on the command and address bus which are used to select an individual memory device or group of memory devices in a bank for an operation.

10. 发明授权

US5935263A Method and apparatus for memory array compressed data testing 失效
标题翻译：存储器阵列压缩数据测试的方法和装置
公开(公告)号：US5935263A
公开(公告)日：1999-08-10
申请号：US886195
申请日：1997-07-01
申请人： Brent Keeth , Troy A. Manning , Chris G. Martin , Kim M. Pierce , Wallace E. Fister , Kevin J. Ryan , Terry R. Lee , Mike Pearson , Thomas W. Voshell
发明人： Brent Keeth , Troy A. Manning , Chris G. Martin , Kim M. Pierce , Wallace E. Fister , Kevin J. Ryan , Terry R. Lee , Mike Pearson , Thomas W. Voshell
IPC分类号： G11C29/38 , G11C29/48 , H03M13/09 , G06F11/00
CPC分类号： H03M13/093 , G11C29/38 , G11C29/48
摘要： A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.
摘要翻译：存储器件包括将数据从耦合到存储器阵列的I / O电路传送到输出三态缓冲器的输出数据路径。比较电路将来自I / O电路的数据与期望的数据模式进行比较。如果数据与所需模式不匹配，则比较电路输出输入到输出缓冲器的错误信号。当输出缓冲器接收到错误信号时，输出缓冲器被禁止，并在数据总线上输出三态条件。由于误差信号对应于多个数据位，所以输出缓冲器的三态条件保持数据时钟的多于一个刻度，而不是仅一个刻度。因此，三态条件保持在总线上足够长，使得测试系统即使在非常高的时钟频率也可以检测三态条件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式