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1. 发明申请

US20070143549A1 System and method for reducing store latency 有权
标题翻译：减少存储延迟的系统和方法
公开(公告)号：US20070143549A1
公开(公告)日：2007-06-21
申请号：US11311751
申请日：2005-12-19
申请人： Bratin Saha , Hariharan Thantry , Ali-Reza Adl-Tabatabai
发明人： Bratin Saha , Hariharan Thantry , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00
CPC分类号： G06F12/0822
摘要： According to one embodiment of the invention, a method comprises verifying that a cache block is not exclusively owned, and if not, transmitting a message identifying both the cache block and a caching agent requesting ownership of the cache block to a broadcast interconnect.
摘要翻译：根据本发明的一个实施例，一种方法包括验证高速缓存块不是专有的，如果没有，则将识别高速缓存块和缓存代理的高速缓存代理的消息发送到广播互连。

2. 发明授权

US08365016B2 Performing mode switching in an unbounded transactional memory (UTM) system 有权
标题翻译：在无界事务内存（UTM）系统中执行模式切换
公开(公告)号：US08365016B2
公开(公告)日：2013-01-29
申请号：US13307492
申请日：2011-11-30
申请人： Jan Gray , Martin Taillefer , Yossi Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod Grover , Mike Magruder , Matt Tolton , Bratin Saha , Gad Sheaffer , Vadim Bassin
发明人： Jan Gray , Martin Taillefer , Yossi Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod Grover , Mike Magruder , Matt Tolton , Bratin Saha , Gad Sheaffer , Vadim Bassin
IPC分类号： G06F11/00
CPC分类号： G06F12/0815 , G06F9/467 , G06F11/141
摘要： In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在具有多个事务执行模式的无界事务存储器（UTM）系统中选择开始第一事务的第一事务执行模式的方法。这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件执行的硬件辅助模式以及软件缓冲器，以及在没有事务性硬件的情况下执行的软件事务存储器（STM）模式。如果在STM模式下没有执行等待事务，则可以将第一事务执行模式选择为硬件模式的最高执行模式，否则可以选择较低的执行模式。描述和要求保护其他实施例。

3. 发明授权

US08185698B2 Hardware acceleration of a write-buffering software transactional memory 有权
公开(公告)号：US08185698B2
公开(公告)日：2012-05-22
申请号：US11784859
申请日：2007-04-09
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3851 , G06F9/3863 , G06F9/467 , G06F12/0842
摘要： A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field associated with a line of the transaction memory is initialized to a first value upon starting a transaction. In response to encountering a read operation in the transaction, then annotation field is checked. If the annotation field includes a first value, the read is serviced from the line of the transaction memory without having to search an additional write space. A second and third value in the annotation field potentially indicates whether a read operation missed the transactional memory or a tentative value is stored in a write space. Additionally, an additional bit in the annotation field, may be utilized to indicate whether previous read operations have been logged, allowing for subsequent redundant read logging to be reduced.

4. 发明申请

US20120066457A1 SYSTEM AND METHOD FOR ALLOCATING AND DEALLOCATING MEMORY WITHIN TRANSACTIONAL CODE 有权
标题翻译：用于在交易代码中分配和分配存储器的系统和方法
公开(公告)号：US20120066457A1
公开(公告)日：2012-03-15
申请号：US13047257
申请日：2011-03-14
申请人： Benjamin C. Hertzberg , Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Benjamin C. Hertzberg , Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/02
CPC分类号： G06F12/023 , G06F9/466 , G06F9/5016 , Y10S707/99943 , Y10S707/99953
摘要： Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.
摘要翻译：提供了方法和系统，用于在事务代码（包括嵌套事务代码）中管理内存分配和释放。方法和系统通过使用标识符（如序列号）来处理事务中的内存管理来管理事务内存操作。方法和系统还维护在事务中止和提交时间执行的延迟操作的列表。与一个或多个事务相关联的多个存储器管理例程检查当前事务的事务序列号，操纵提交和/或撤销日志，以及设置/使用关联对象的事务序列号，但不限于此。方法和系统在事务代码中提供内存分配和释放，同时保留事务语义。描述和要求保护其他实施例。

5. 发明授权

US08108627B2 Array comparison and swap operations 有权
标题翻译：数组比较和交换操作
公开(公告)号：US08108627B2
公开(公告)日：2012-01-31
申请号：US11395410
申请日：2006-03-31
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00 , G06F11/00
CPC分类号： G06F9/526
摘要： A transactional memory system, method and apparatus are disclosed. An embodiment of the method includes attempting to acquire a write lock provided by an implementation of a software transactional memory (STM) system for each of a set of memory locations of the STM; if a write lock is acquired for each of the set of memory locations, comparing the value in each of the set of memory locations to a corresponding expected value; and if the comparing yields the same, predetermined result for each of the set of memory locations, storing in each memory location a corresponding new value. Other embodiments are also described and claimed.
摘要翻译：公开了事务性存储器系统，方法和装置。该方法的实施例包括尝试获取由STM的一组存储器位置中的每一个的软件事务存储器（STM）系统的实现提供的写锁定; 如果针对所述一组存储器单元中的每一个获取写锁定，则将所述一组存储器位置中的每一个的值与相应的预期值进行比较; 并且如果比较产生相同的存储器位置集合中的每一个的预定结果，则在每个存储器位置存储相应的新值。还描述和要求保护其他实施例。

6. 发明申请

US20120016853A1 EFFICIENT AND CONSISTENT SOFTWARE TRANSACTIONAL MEMORY 有权
标题翻译：有效和一致的软件交易记忆
公开(公告)号：US20120016853A1
公开(公告)日：2012-01-19
申请号：US13246678
申请日：2011-09-27
申请人： Cheng Wang , Youfeng Wu , Wei-Yu Chen , Bratin Saha , Ali Reza Adl-Tabatabai
发明人： Cheng Wang , Youfeng Wu , Wei-Yu Chen , Bratin Saha , Ali Reza Adl-Tabatabai
IPC分类号： G06F7/00
CPC分类号： G06F8/458 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863 , G06F9/467
摘要： A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.
摘要翻译：这里描述了用于在软件事务存储器（STM）系统中有效且一致的验证/冲突检测的方法和装置。在加载之后插入版本检查障碍，以便在加载之前和之后比较加载值的版本。此外，使用全局时间戳（GTS）来跟踪最近提交的事务。每个事务与在事务开始时初始化为GTS值的本地时间戳（LTS）相关联。作为事务提交，将GTS更新为新值，并将修改的位置的版本设置为新值。待处理的交易将比较其在LTS阅读障碍中确定的版本。如果版本大于其LTS，指示在挂起事务启动并初始化LTS之后另一个事务已经提交，则挂起的事务会验证其读取集合以保持有效且一致的事务执行。

7. 发明授权

US08086827B2 Mechanism for irrevocable transactions 有权
标题翻译：不可撤销交易的机制
公开(公告)号：US08086827B2
公开(公告)日：2011-12-27
申请号：US11648485
申请日：2006-12-28
申请人： Adam Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Adam Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/30
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087 , G06F9/3857 , G06F9/3863
摘要： A method and apparatus for designating and handling irrevocable transaction is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designated as irrevocable. In response to designating a transaction as irrevocable, Single Owner Read Locks (SORLs) are acquired for previous and subsequent reads in the irrevocably designated transaction to ensure the transaction is able to complete without modification to locations read from, while permitting remote resources to load from those locations to continue execution.
摘要翻译：这里描述用于指定和处理不可撤销交易的方法和装置。响应于检测到诸如I / O操作，用户定义的不可撤销指定和动态故障简档的不可撤销事件，交易被指定为不可撤销。为了将交易指定为不可撤销，单独所有者读取锁（SORL）是为不可撤销地指定的事务中的先前和后续读取而获取的，以确保事务能够完成，而无需修改读取的位置，同时允许远程资源从那些位置继续执行。

8. 发明授权

US07802059B2 Object based conflict detection in a software transactional memory 有权
标题翻译：软件事务内存中基于对象的冲突检测
公开(公告)号：US07802059B2
公开(公告)日：2010-09-21
申请号：US12270710
申请日：2008-11-13
申请人： Ben Hertzberg , Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Ben Hertzberg , Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/14 , G06F12/02
CPC分类号： G06F9/524
摘要： Object-based conflict detection is described in the context of software transactional memory. In one example, a pointer is received for a block of instructions, the block of instructions having allocated objects. The lower bits of the pointer are masked if the pointer is in a small object space to obtain a block header for the block, and a size of the allocated objects is determined using the block header.
摘要翻译：基于对象的冲突检测在软件事务内存的上下文中进行了描述。在一个示例中，针对指令块接收指针，该指令块具有分配的对象。如果指针位于小对象空间中以获取块的块头，则指示符的较低位被屏蔽，并且使用块头来确定分配的对象的大小。

9. 发明申请

US20100153953A1 UNIFIED OPTIMISTIC AND PESSIMISTIC CONCURRENCY CONTROL FOR A SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEM 有权
标题翻译：用于软件交易存储器（STM）系统的统一的最佳和适用的汇率控制
公开(公告)号：US20100153953A1
公开(公告)日：2010-06-17
申请号：US12337507
申请日：2008-12-17
申请人： Ali-Reza Adl-Tabatabai , Moshe Bach , Sion Berkowits , James Henry Cownie , Yang Ni , Jeffrey V. Olivier , Bratin Saha , Ady Tal , Adam Wele
发明人： Ali-Reza Adl-Tabatabai , Moshe Bach , Sion Berkowits , James Henry Cownie , Yang Ni , Jeffrey V. Olivier , Bratin Saha , Ady Tal , Adam Wele
IPC分类号： G06F9/46
CPC分类号： G06F9/467 , G06F9/528 , G06F17/30351 , G06F17/30353 , G06F17/30356 , G06F17/30359
摘要： A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
摘要翻译：这里描述了用于软件事务存储器（STM）中的统一并发控制的方法和装置。与由事务性存储器访问操作引用的存储器地址相关联的事务记录包括乐观和悲观的并发控制字段。利用访问障碍和其他交易操作/功能来适当地维护交易记录的两个领域。因此，同时执行乐观和悲观的交易得以实现。

10. 发明申请

US20100058344A1 ACCELERATING A QUIESCENCE PROCESS OF TRANSACTIONAL MEMORY 审中-公开
标题翻译：加快交易记忆质量的过程
公开(公告)号：US20100058344A1
公开(公告)日：2010-03-04
申请号：US12198820
申请日：2008-08-26
申请人： Yang Ni , Richard Myungon Yoo , Adam Wojciech Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Yang Ni , Richard Myungon Yoo , Adam Wojciech Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/46 , G06F17/30 , G06F7/00
CPC分类号： G06F9/466
摘要： A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions.
摘要翻译：提出了一种执行事务读取集验证的方法。在一个实施例中，该方法将事务的读取签名与与多个事务相关联的多个写入签名进行比较。该方法基于比较结果确定是否将交易的本地值更新为来自多个交易的另一事务的提交值。

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