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1. 发明授权

US07745876B2 Semiconductor integrated circuit devices including gate patterns having step difference therebetween and a connection line disposed between the gate patterns and methods of fabricating the same 有权
标题翻译：半导体集成电路器件包括具有阶梯差的栅极图案和设置在栅极图案之间的连接线及其制造方法
公开(公告)号：US07745876B2
公开(公告)日：2010-06-29
申请号：US11852940
申请日：2007-09-10
申请人： Bong-Soo Kim , Hyeong-Sun Hong , Soo-Ho Shin , Ho-In Ryu
发明人： Bong-Soo Kim , Hyeong-Sun Hong , Soo-Ho Shin , Ho-In Ryu
IPC分类号： H01L27/108
CPC分类号： H01L29/78 , H01L27/0207 , H01L27/10805 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/7833
摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.
摘要翻译：提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。单元栅极图案设置在单元有源区和器件隔离层上。外围栅极图案设置在外围有源区域上。电池电节点设置在与电池栅极图案相邻的电池有源区域上。外围电节点设置在与外围栅极图案相邻的外围有源区域上。连接线设置在设置在器件隔离层上的单元栅极图案上。连接线连接在单元栅极图案和外围栅极图案之间。

2. 发明申请

US20100221875A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING GATE PATTERNS HAVING STEP DIFFERENCE THEREBETWEEN AND A CONNECTION LINE DISPOSED BETWEEN THE GATE PATTERNS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体集成电路装置，其中包括具有步骤差异的栅格图案和栅格图案之间处理的连接线及其制造方法
公开(公告)号：US20100221875A1
公开(公告)日：2010-09-02
申请号：US12781859
申请日：2010-05-18
申请人： Bong-Soo Kim , Hyeong-Sun Hong , Soo-Ho Shin , Ho-In Ryu
发明人： Bong-Soo Kim , Hyeong-Sun Hong , Soo-Ho Shin , Ho-In Ryu
IPC分类号： H01L21/82
CPC分类号： H01L29/78 , H01L27/0207 , H01L27/10805 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/7833
摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.
摘要翻译：提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。单元栅极图案设置在单元有源区和器件隔离层上。外围栅极图案设置在外围有源区域上。电池电节点设置在与电池栅极图案相邻的电池有源区域上。外围电节点设置在与外围栅极图案相邻的外围有源区域上。连接线设置在设置在器件隔离层上的单元栅极图案上。连接线连接在单元栅极图案和外围栅极图案之间。

3. 发明申请

US20080197393A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING GATE PATTERNS HAVING STEP DIFFERENCE THEREBETWEEN AND A CONNECTION LINE DISPOSED BETWEEN THE GATE PATTERNS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体集成电路装置，其中包括具有步骤差异的栅格图案和栅格图案之间处理的连接线及其制造方法
公开(公告)号：US20080197393A1
公开(公告)日：2008-08-21
申请号：US11852940
申请日：2007-09-10
申请人： Bong-Soo Kim , Hyeong-Sun Hong , Soo-Ho Shin , Ho-In Ryu
发明人： Bong-Soo Kim , Hyeong-Sun Hong , Soo-Ho Shin , Ho-In Ryu
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/78 , H01L27/0207 , H01L27/10805 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/7833
摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.
摘要翻译：提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。单元栅极图案设置在单元有源区和器件隔离层上。外围栅极图案设置在外围有源区域上。电池电节点设置在与电池栅极图案相邻的电池有源区域上。外围电节点设置在与外围栅极图案相邻的外围有源区域上。连接线设置在设置在器件隔离层上的单元栅极图案上。连接线连接在单元栅极图案和外围栅极图案之间。

4. 发明授权

US08872262B2 Semiconductor integrated circuit devices including gates having connection lines thereon 有权
标题翻译：包括其上具有连接线的门的半导体集成电路器件
公开(公告)号：US08872262B2
公开(公告)日：2014-10-28
申请号：US12781859
申请日：2010-05-18
申请人： Bong-Soo Kim , Hyeong-Sun Hong , Soo-Ho Shin , Ho-In Ryu
发明人： Bong-Soo Kim , Hyeong-Sun Hong , Soo-Ho Shin , Ho-In Ryu
IPC分类号： H01L27/108 , H01L27/02 , H01L29/78
CPC分类号： H01L29/78 , H01L27/0207 , H01L27/10805 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/7833
摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.
摘要翻译：提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。单元栅极图案设置在单元有源区和器件隔离层上。外围栅极图案设置在外围有源区域上。电池电节点设置在与电池栅极图案相邻的电池有源区域上。外围电节点设置在与外围栅极图案相邻的外围有源区域上。连接线设置在设置在器件隔离层上的单元栅极图案上。连接线连接在单元栅极图案和外围栅极图案之间。

5. 发明授权

US07595529B2 Semiconductor integrated circuit devices having upper pattern aligned with lower pattern molded by semiconductor substrate and methods of forming the same 有权
标题翻译：具有与由半导体衬底模制的下部图案对准的上部图案的半导体集成电路器件及其形成方法
公开(公告)号：US07595529B2
公开(公告)日：2009-09-29
申请号：US12176263
申请日：2008-07-18
申请人： Bong-Soo Kim , Hyeong-Sun Hong , Soo-Ho Shin , Ho-In Ryu
发明人： Bong-Soo Kim , Hyeong-Sun Hong , Soo-Ho Shin , Ho-In Ryu
IPC分类号： H01L21/768
CPC分类号： H01L29/78 , H01L27/0207 , H01L27/10805 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/7833
摘要： Provided are semiconductor integrated circuit (IC) devices having an upper pattern aligned with a lower pattern molded by a semiconductor substrate and methods of forming the same. In the semiconductor IC devices, the lower pattern contacts the upper pattern using an active region and/or an isolation layer. The methods include preparing a semiconductor substrate having an active region. A lower pattern is formed on the active region. The lower pattern is surrounded by the active region and protrudes from a top surface of the active region. An upper pattern is disposed on the lower pattern. The upper pattern contacts the lower pattern.
摘要翻译：提供了具有与由半导体衬底模制的下部图案对准的上部图案的半导体集成电路（IC）器件及其形成方法。在半导体IC器件中，下图案使用有源区和/或隔离层接触上图案。所述方法包括制备具有活性区域的半导体衬底。在有源区上形成较低的图案。下图案被有源区域包围并从有源区域的顶表面突出。上部图案设置在下部图案上。上部图案接触下部图案。

6. 发明授权

US08502341B2 Trench-type capacitor, semiconductor device having the same, and semiconductor module having the semiconductor device 有权
标题翻译：沟槽型电容器，具有该沟槽型电容器的半导体器件和具有半导体器件的半导体模块
公开(公告)号：US08502341B2
公开(公告)日：2013-08-06
申请号：US13021333
申请日：2011-02-04
申请人： Chul Lee , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
发明人： Chul Lee , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
IPC分类号： H01L29/92
CPC分类号： H01L29/92
摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.
摘要翻译：提供了沟槽型电容器。为了形成电容器，第一和第二有源区域设置在半导体衬底中。节点图案设置在第一活动区域中。每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。杂质扩散区域设置在节点图案附近。设置与第一和第二有源区电接触的衬底连接图案。与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

7. 发明申请

US20110210421A1 TRENCH-TYPE CAPACITOR, SEMICONDUCTOR DEVICE HAVING THE SAME, AND SEMICONDUCTOR MODULE HAVING THE SEMICONDUCTOR DEVICE 有权
标题翻译： TRENCH型电容器，具有它们的半导体器件和具有半导体器件的半导体器件
公开(公告)号：US20110210421A1
公开(公告)日：2011-09-01
申请号：US13021333
申请日：2011-02-04
申请人： CHUL LEE , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
发明人： CHUL LEE , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
IPC分类号： H01L29/92
CPC分类号： H01L29/92
摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.
摘要翻译：提供了沟槽型电容器。为了形成电容器，第一和第二有源区域设置在半导体衬底中。节点图案设置在第一活动区域中。每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。杂质扩散区域设置在节点图案附近。设置与第一和第二有源区电接触的衬底连接图案。与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

8. 发明申请

US20100193880A1 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20100193880A1
公开(公告)日：2010-08-05
申请号：US12662150
申请日：2010-04-01
申请人： Makoto Yoshida , Hyeong-Sun Hong , Kye-Hee Yeom , Dae-Ik Kim , Yong-Il Kim
发明人： Makoto Yoshida , Hyeong-Sun Hong , Kye-Hee Yeom , Dae-Ik Kim , Yong-Il Kim
IPC分类号： H01L23/52 , H01L27/088
CPC分类号： H01L27/10894 , H01L21/82345 , H01L21/823456 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L29/4236 , H01L29/66621
摘要： A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.
摘要翻译：半导体器件及其形成方法包括在半导体衬底上形成单元位线图案和外围栅极图案。单元位线图案可以形成在与半导体基板的单元有源区域相邻的非活性区域上。外围栅极图案可以设置在半导体衬底的外围有源区上。细胞接触插塞可以形成在细胞位线图案和细胞活性区域之间。周边接触插塞可以形成在外围栅极图案侧的外围有源区域上。可以形成绝缘层，以将电池位线图形，外围栅极图案，电池和外围接触插头的顶表面暴露在基本上相同的水平。

9. 发明申请

US20080284029A1 Contact structures and semiconductor devices including the same and methods of forming the same 有权
标题翻译：接触结构和包括其的半导体器件及其形成方法
公开(公告)号：US20080284029A1
公开(公告)日：2008-11-20
申请号：US12151997
申请日：2008-05-12
申请人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
发明人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L29/4236 , H01L21/76829 , H01L21/76897 , H01L27/0207 , H01L27/10855 , H01L27/10876
摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.
摘要翻译：在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。在半导体衬底上形成第一层间电介质层。形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。在包括位线结构的半导体衬底上形成第二层间电介质层。阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成埋入的接触孔，并且在埋入的接触孔中形成掩埋的接触插塞。

10. 发明授权

US08378497B2 Contact structures and semiconductor devices including the same 有权
标题翻译：接触结构和包括其的半导体器件
公开(公告)号：US08378497B2
公开(公告)日：2013-02-19
申请号：US12758946
申请日：2010-04-13
申请人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
发明人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/4236 , H01L21/76829 , H01L21/76897 , H01L27/0207 , H01L27/10855 , H01L27/10876
摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.
摘要翻译：在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。在半导体衬底上形成第一层间电介质层。形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。在包括位线结构的半导体衬底上形成第二层间电介质层。阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成埋入的接触孔，并且在埋入的接触孔中形成掩埋的接触插塞。

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