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1. 发明申请

US20130178010A1 METHOD OF FORMING A METAL PATTERN AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE 审中-公开
标题翻译：形成金属图案的方法和制造显示基板的方法
公开(公告)号：US20130178010A1
公开(公告)日：2013-07-11
申请号：US13585255
申请日：2012-08-14
申请人： Bong-Kyun KIM , Wang-Woo Lee , Shin Il Choi , Hong-Sick Park , Young-Woo Park
发明人： Bong-Kyun KIM , Wang-Woo Lee , Shin Il Choi , Hong-Sick Park , Young-Woo Park
IPC分类号： C23F1/14 , B05D3/00 , H01L33/08
CPC分类号： H01L27/1288 , C23F1/18 , C23F1/26 , H01L21/02071 , H01L21/32134 , H01L27/124
摘要： A method of forming a metal pattern is provided. In the method, a first titanium layer, a copper layer and a second titanium layer are sequentially formed on a substrate. A photo pattern is formed on the second titanium layer. The first titanium layer, the copper layer and the second titanium layer are patterned using the photo pattern to form a first titanium pattern, a copper pattern formed on the first titanium pattern and a second titanium pattern formed on the copper pattern. Therefore, a fine metal pattern may be formed.
摘要翻译：提供了形成金属图案的方法。在该方法中，在基板上依次形成第一钛层，铜层和第二钛层。在第二钛层上形成照片图案。使用照片图案对第一钛层，铜层和第二钛层进行图案化，以形成第一钛图案，形成在第一钛图案上的铜图案和形成在铜图案上的第二钛图案。因此，可以形成精细的金属图案。

2. 发明授权

US08198157B2 Methods of forming non-volatile memory devices including dummy word lines 有权
标题翻译：形成包括虚拟字线的非易失性存储器件的方法
公开(公告)号：US08198157B2
公开(公告)日：2012-06-12
申请号：US13236913
申请日：2011-09-20
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： H01L21/82 , H01L21/336 , H01L21/4763 , H01L21/44
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。还讨论了相关方法。

3. 发明申请

US20120045890A1 Methods Of Forming Non-Volatile Memory Devices Including Dummy Word Lines 有权
标题翻译：形成包含虚拟字线的非易失性存储器件的方法
公开(公告)号：US20120045890A1
公开(公告)日：2012-02-23
申请号：US13236913
申请日：2011-09-20
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： H01L21/28
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。还讨论了相关方法。

4. 发明授权

US08048746B2 Method of making flash memory cells and peripheral circuits having STI, and flash memory devices and computer systems having the same 失效
公开(公告)号：US08048746B2
公开(公告)日：2011-11-01
申请号：US12979890
申请日：2010-12-28
申请人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
发明人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11546 , H01L27/11592 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.

5. 发明申请

US20090315099A1 METHOD OF MAKING FLASH MEMORY CELLS AND PERIPHERAL CIRCUITS HAVING STI, AND FLASH MEMORY DEVICES AND COMPUTER SYSTEMS HAVING THE SAME 有权
标题翻译：制造闪速存储器细胞的方法和具有STI的外围电路以及具有该闪存存储器的闪速存储器件和计算机系统
公开(公告)号：US20090315099A1
公开(公告)日：2009-12-24
申请号：US12367988
申请日：2009-02-09
申请人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
发明人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
IPC分类号： H01L25/07 , H01L21/76
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11546 , H01L27/11592 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.
摘要翻译：集成电路包括闪存单元，以及包括低压晶体管（LVT）和高压晶体管（HVT））的外围电路。集成电路包括包含SiON，SiN或其它高k材料的隧道势垒层。隧道势垒层可以包括HVT的栅极电介质的一部分。隧道势垒层可以构成HVT的整个栅电介质。相应的隧道势垒层可以形成在浅沟槽隔离（STI）之间或之间。因此，可以提高驱动器芯片IC的制造效率。

6. 发明申请

US20090212340A1 FLASH MEMORY DEVICES 审中-公开
标题翻译：闪存存储器件
公开(公告)号：US20090212340A1
公开(公告)日：2009-08-27
申请号：US12392656
申请日：2009-02-25
申请人： Chang-Hyun Lee , Young-Woo Park , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park
发明人： Chang-Hyun Lee , Young-Woo Park , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/11521
摘要： A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region.
摘要翻译：一种栅极电极线，其在包括由器件隔离层限定并在第一方向上延伸的有源区域和设置在有源区域和栅电极线之间的电荷陷阱层的基板上沿与第一方向交叉的第二方向延伸其特征在于，设置在所述器件隔离层上的所述栅电极线的底面低于设置在所述有源区上并高于所述有源区的顶面的所述电荷陷阱层的顶面。

7. 发明申请

US20070259505A1 NON-VOLATILE MEMORY DEVICES AND METHODS FOR FORMING THE SAME 审中-公开
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20070259505A1
公开(公告)日：2007-11-08
申请号：US11613329
申请日：2006-12-20
申请人： Young-Woo Park , Jung-Dal Choi
发明人： Young-Woo Park , Jung-Dal Choi
IPC分类号： H01L21/02
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11568
摘要： Non-volatile memory devices and methods for forming the same are provided. A device isolation layer may be formed on the semiconductor substrate to define an active region. A tunneling insulation pattern, a charge storage pattern, and a blocking insulation pattern may be disposed on the active region. A gate electrode may be disposed on the blocking insulation pattern. The charge storage pattern may be arranged in a matrix and a lower surface thereof is higher than an upper surface of the device isolation layer.
摘要翻译：提供非易失性存储器件及其形成方法。可以在半导体衬底上形成器件隔离层以限定有源区。隧道绝缘图案，电荷存储图案和阻挡绝缘图案可以设置在有源区域上。栅电极可以设置在阻挡绝缘图案上。电荷存储图案可以布置成矩阵并且其下表面高于器件隔离层的上表面。

8. 发明授权

US06777343B2 Method of forming contacts for a bit line and a storage node in a semiconductor device 有权
标题翻译：在半导体器件中形成位线和存储节点的触点的方法
公开(公告)号：US06777343B2
公开(公告)日：2004-08-17
申请号：US10256438
申请日：2002-09-26
申请人： Young-Woo Park , Won-Sung Lee
发明人： Young-Woo Park , Won-Sung Lee
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L23/485 , H01L27/0207 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A method of forming self-aligned contact holes in an oxide layer to expose a semiconductor substrate between adjacent gate lines. The gate lines are formed such that a spacing between adjacent gate lines in the storage node contact region is equal to or greater than a spacing between adjacent gate lines in the bit line contact region. An insulating layer is deposited on the gate line to fill spaces between the gate lines. Self-aligned contact holes are formed in the insulating layer, using a photolithographic process. As a result, storage node contact hole not-opening phenomenon and bit line contact shoulder over-etching phenomenon can be avoided.
摘要翻译：在氧化物层中形成自对准接触孔以在相邻栅极线之间露出半导体衬底的方法。栅极线形成为使得存储节点接触区域中的相邻栅极线之间的间隔等于或大于位线接触区域中的相邻栅极线之间的间隔。绝缘层沉积在栅极线上以填充栅极线之间的空间。使用光刻工艺在绝缘层中形成自对准的接触孔。结果，可以避免存储节点接触孔不开现象和位线接触肩部过蚀刻现象。

9. 发明授权

US09577115B2 Semiconductor devices having air gaps 有权
标题翻译：具有气隙的半导体器件
公开(公告)号：US09577115B2
公开(公告)日：2017-02-21
申请号：US13195347
申请日：2011-08-01
申请人： Byung-Kyu Cho , Chang-Hyun Lee , Young-Woo Park
发明人： Byung-Kyu Cho , Chang-Hyun Lee , Young-Woo Park
IPC分类号： H01L21/70 , H01L29/788 , H01L21/764 , H01L27/115 , H01L29/423
CPC分类号： H01L29/7881 , H01L21/764 , H01L27/11521 , H01L29/42336
摘要： A semiconductor device has an isolation layer pattern, a plurality of gate structures, and a first insulation layer pattern. The isolation layer pattern is formed on a substrate and has a recess thereon. The gate structures are spaced apart from each other on the substrate and the isolation layer pattern. The first insulation layer pattern is formed on the substrate and covers the gate structures and an inner wall of the recess. The first insulation layer pattern has a first air gap therein.
摘要翻译：半导体器件具有隔离层图案，多个栅极结构和第一绝缘层图案。隔离层图案形成在基板上并且在其上具有凹部。栅极结构在衬底和隔离层图案上彼此间隔开。第一绝缘层图案形成在基板上并且覆盖该凹槽的栅极结构和内壁。第一绝缘层图案中具有第一气隙。

10. 发明授权

US08546870B2 Semiconductor devices having gate structures with conductive patterns of different widths and methods of fabricating such devices 有权
标题翻译：具有具有不同宽度的导电图案的栅极结构的半导体器件和制造这种器件的方法
公开(公告)号：US08546870B2
公开(公告)日：2013-10-01
申请号：US12622594
申请日：2009-11-20
申请人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
发明人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L29/4234
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括依次层叠在半导体衬底上的第一电介质图案，数据存储图案和第二电介质图案。在第二电介质图案上提供第一导电图案。具有比第一导电图案更大的宽度的第二导电图案设置在第一导电图案上。

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