专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08921816B2 Semiconductor device having a diode 有权
标题翻译：具有二极管的半导体器件
公开(公告)号：US08921816B2
公开(公告)日：2014-12-30
申请号：US13178762
申请日：2011-07-08
申请人： Bo-Young Seo , Byung-Suo Shim , Yong-Kyu Lee , Tea-Kwang Yu , Ji-Hoon Park
发明人： Bo-Young Seo , Byung-Suo Shim , Yong-Kyu Lee , Tea-Kwang Yu , Ji-Hoon Park
IPC分类号： H01L29/02 , H01L27/24 , H01L27/102 , H01L45/00
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/06
摘要： Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.
摘要翻译：提供一种半导体器件。该半导体器件包括半导体衬底上的下部有源区。提供从下部有源区域的顶表面突出并且具有比下部有源区域更窄的多个上部有源区域。提供了围绕下部有源区域的侧壁的下部隔离区域。提供了形成在下隔离区域上的上隔离区域，其围绕上活性区域的侧壁，并且具有比下隔离区域窄的宽度。提供形成在下部有源区并延伸到上部有源区的第一杂质区。提供形成在上部有源区并与第一杂质区一起构成二极管的第二杂质区。还提供了制造该方法的方法。

2. 发明申请

US20120007212A1 SEMICONDUCTOR DEVICE HAVING A DIODE 有权
标题翻译：具有二极管的半导体器件
公开(公告)号：US20120007212A1
公开(公告)日：2012-01-12
申请号：US13178762
申请日：2011-07-08
申请人： Bo-Young SEO , Byung-Suo Shim , Yong-Kyu Lee , Tea-Kwang Yu , Ji-Hoon Park
发明人： Bo-Young SEO , Byung-Suo Shim , Yong-Kyu Lee , Tea-Kwang Yu , Ji-Hoon Park
IPC分类号： H01L29/06
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/06
摘要： Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.
摘要翻译：提供一种半导体器件。该半导体器件包括半导体衬底上的下部有源区。提供从下部有源区域的顶表面突出并且具有比下部有源区域更窄的多个上部有源区域。提供了围绕下部有源区域的侧壁的下部隔离区域。提供了形成在下隔离区域上的上隔离区域，其围绕上活性区域的侧壁，并且具有比下隔离区域窄的宽度。提供形成在下部有源区并延伸到上部有源区的第一杂质区。提供形成在上部有源区并与第一杂质区一起构成二极管的第二杂质区。还提供了制造该方法的方法。

3. 发明授权

US08526231B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08526231B2
公开(公告)日：2013-09-03
申请号：US13177873
申请日：2011-07-07
申请人： Yong-Kyu Lee , Tea-Kwang Yu , Bo-Young Seo
发明人： Yong-Kyu Lee , Tea-Kwang Yu , Bo-Young Seo
IPC分类号： G11C11/34
CPC分类号： G11C16/0408 , G11C16/0425 , G11C16/06 , G11C16/3418
摘要： A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.
摘要翻译：非易失性存储器件包括第一扇区，包括第一扇区选择晶体管和连接到第一扇区选择晶体管的第一多个页，以及包括第二扇区选择晶体管的第二扇区和连接到第二扇区选择晶体管的第二多个页扇区选择晶体管。第一和第二多页中的每一页包括存储晶体管和选择晶体管，并且第一多页中的页数大于第二多页中的页数。

4. 发明申请

US20120070949A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及半导体器件制造方法
公开(公告)号：US20120070949A1
公开(公告)日：2012-03-22
申请号：US13180613
申请日：2011-07-12
申请人： Tea-Kwang Yu , Byung-Sup Shim , Yong-Kyu Lee , Bo-Young Seo , Yong-Tae Kim
发明人： Tea-Kwang Yu , Byung-Sup Shim , Yong-Kyu Lee , Bo-Young Seo , Yong-Tae Kim
IPC分类号： H01L21/8239 , H01L21/8229
CPC分类号： H01L27/2436 , H01L27/105 , H01L27/2445 , H01L45/1683
摘要： A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.
摘要翻译：一种制造半导体器件的方法包括提供具有存储块和在其中定义的逻辑块的衬底，在存储块上形成伪栅极图案; 在伪栅极图案的一侧形成第一导电类型的第一区域和在虚拟栅极图案的另一侧形成第二导电类型的第二区域，以及形成与第一区域电连接的非易失性存储器件。

5. 发明授权

US08476130B2 Semiconductor device and method of fabricating semiconductor device 有权
标题翻译：半导体器件及半导体器件的制造方法
公开(公告)号：US08476130B2
公开(公告)日：2013-07-02
申请号：US13180613
申请日：2011-07-12
申请人： Tea-Kwang Yu , Byung-Sup Shim , Yong-Kyu Lee , Bo-Young Seo , Yong-Tae Kim
发明人： Tea-Kwang Yu , Byung-Sup Shim , Yong-Kyu Lee , Bo-Young Seo , Yong-Tae Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/2436 , H01L27/105 , H01L27/2445 , H01L45/1683
摘要： A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.
摘要翻译：一种制造半导体器件的方法包括提供具有存储块和在其中定义的逻辑块的衬底，在存储块上形成伪栅极图案; 在伪栅极图案的一侧形成第一导电类型的第一区域和在虚拟栅极图案的另一侧形成第二导电类型的第二区域，以及形成与第一区域电连接的非易失性存储器件。

6. 发明申请

US20120087189A1 Non-Volatile Memory Device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20120087189A1
公开(公告)日：2012-04-12
申请号：US13177873
申请日：2011-07-07
申请人： Yong-Kyu Lee , Tea-Kwang Yu , Bo-Young Seo
发明人： Yong-Kyu Lee , Tea-Kwang Yu , Bo-Young Seo
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G11C16/0425 , G11C16/06 , G11C16/3418
摘要： A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.
摘要翻译：非易失性存储器件包括第一扇区，包括第一扇区选择晶体管和连接到第一扇区选择晶体管的第一多个页，以及包括第二扇区选择晶体管的第二扇区和连接到第二扇区选择晶体管的第二多个页扇区选择晶体管。第一和第二多页中的每一页包括存储晶体管和选择晶体管，并且第一多页中的页数大于第二多页中的页数。

7. 发明授权

US09275746B2 Source line floating circuits, memory devices including the same and methods of reading data in a memory device 有权
标题翻译：源极线浮动电路，包括相同的存储器件以及在存储器件中读取数据的方法
公开(公告)号：US09275746B2
公开(公告)日：2016-03-01
申请号：US14208200
申请日：2014-03-13
申请人： Chang-Min Jeon , Bo-Young Seo , Tea-Kwang Yu
发明人： Chang-Min Jeon , Bo-Young Seo , Tea-Kwang Yu
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15 , G11C16/24 , G11C16/26 , G11C16/08 , G11C11/16 , G11C13/00
CPC分类号： G11C16/24 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/08 , G11C16/26 , G11C2213/79 , G11C2213/82
摘要： A source line floating circuit includes a plurality of floating units. The floating units directly receive decoded row address signals or voltages of word lines as floating control signals, respectively. The decoded row address signals are activated selectively in response to a row address signal. The floating units control electrical connections between source lines and a source voltage in response to the floating control signals in a read operation. Related devices and methods are also described.
摘要翻译：源极线浮置电路包括多个浮动单元。浮动单元分别直接接收解码的行地址信号或字线的电压作为浮动控制信号。解码的行地址信号响应于行地址信号被选择性地激活。浮动单元响应于读操作中的浮动控制信号来控制源线之间的电连接和源极电压。还描述了相关的装置和方法。

8. 发明申请

US20140269064A1 SOURCE LINE FLOATING CIRCUITS, MEMORY DEVICES INCLUDING THE SAME AND METHODS OF READING DATA IN A MEMORY DEVICE 有权
标题翻译：源线浮动电路，包括其的存储器件和在存储器件中读取数据的方法
公开(公告)号：US20140269064A1
公开(公告)日：2014-09-18
申请号：US14208200
申请日：2014-03-13
申请人： Chang-Min Jeon , Bo-Young Seo , Tea-Kwang Yu
发明人： Chang-Min Jeon , Bo-Young Seo , Tea-Kwang Yu
IPC分类号： G11C16/24 , G11C16/26
CPC分类号： G11C16/24 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/08 , G11C16/26 , G11C2213/79 , G11C2213/82
摘要： A source line floating circuit includes a plurality of floating units. The floating units directly receive decoded row address signals or voltages of word lines as floating control signals, respectively. The decoded row address signals are activated selectively in response to a row address signal. The floating units control electrical connections between source lines and a source voltage in response to the floating control signals in a read operation. Related devices and methods are also described.
摘要翻译：源极线浮置电路包括多个浮动单元。浮动单元分别直接接收解码的行地址信号或字线的电压作为浮动控制信号。解码的行地址信号响应于行地址信号被选择性地激活。浮动单元响应于读操作中的浮动控制信号来控制源线之间的电连接和源极电压。还描述了相关的装置和方法。

9. 发明授权

US07863110B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07863110B2
公开(公告)日：2011-01-04
申请号：US11907994
申请日：2007-10-19
申请人： Tea-Kwang Yu , Kong-Sam Jang , Kwang-Tae Kim , Ji-Hoon Park , Eun-Mi Hong
发明人： Tea-Kwang Yu , Kong-Sam Jang , Kwang-Tae Kim , Ji-Hoon Park , Eun-Mi Hong
IPC分类号： H01L21/332 , H01L31/119 , H01L23/58
CPC分类号： H01L29/861 , H01L21/76224 , H01L27/105 , H01L27/1052
摘要： A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.
摘要翻译：半导体器件包括在半导体衬底上限定半导体衬底中的有源区的器件隔离层，在半导体衬底的有源区中具有第一导电类型的低电压阱，第二导电类型的高电压杂质区半导体衬底的有源区，位于低压阱上部的高电压杂质区，高电压杂质区内的第二导电类型的高浓度杂质区，与器件隔离层间隔开;以及在器件隔离层和高浓度杂质区之间的第一导电类型的浮置杂质区，浮置杂质区是有源区的上表面的一部分。

10. 发明申请

US20080093701A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080093701A1
公开(公告)日：2008-04-24
申请号：US11907994
申请日：2007-10-19
申请人： Tea-Kwang Yu , Kong-Sam Jang , Kwang-Tae Kim , Ji-Hoon Park , Eun-Mi Hong
发明人： Tea-Kwang Yu , Kong-Sam Jang , Kwang-Tae Kim , Ji-Hoon Park , Eun-Mi Hong
IPC分类号： H01L29/00 , H01L21/761
CPC分类号： H01L29/861 , H01L21/76224 , H01L27/105 , H01L27/1052
摘要： A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.
摘要翻译：半导体器件包括在半导体衬底上限定半导体衬底中的有源区的器件隔离层，在半导体衬底的有源区中具有第一导电类型的低电压阱，第二导电类型的高电压杂质区半导体衬底的有源区，位于低压阱上部的高电压杂质区，高电压杂质区内的第二导电类型的高浓度杂质区，与器件隔离层间隔开;以及在器件隔离层和高浓度杂质区之间的第一导电类型的浮置杂质区，浮置杂质区是有源区的上表面的一部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式