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1. 发明申请

US20120018797A1 NONVOLATILE MEMORY DEVICE, AND METHODS OF MANUFACTURING AND DRIVING THE SAME 审中-公开
标题翻译：非易失性存储器件及其制造和驱动方法
公开(公告)号：US20120018797A1
公开(公告)日：2012-01-26
申请号：US13168257
申请日：2011-06-24
申请人： Tea-Kwang YU , Yong-Tae KIM , Byung-Sup SHIM , Yong-Kyu LEE , Bo-Young SEO , Ji-Hoon PARK
发明人： Tea-Kwang YU , Yong-Tae KIM , Byung-Sup SHIM , Yong-Kyu LEE , Bo-Young SEO , Ji-Hoon PARK
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28518 , H01L21/743 , H01L21/76224 , H01L21/76895 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A nonvolatile memory device includes a device isolation film defining an active region in a semiconductor substrate, a pocket well region formed in an upper portion of the active region and having a first conductivity type, a gate electrode formed on the active region and extending to intersect the active region, a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially disposed between the active region and the gate electrode, a source region and a drain region respectively formed in a first region and a second region of the active region exposed on both sides of the gate electrode, and each having a second conductivity type opposite to the first conductivity type, a pocket well junction region formed in the first region adjacent to the source region and contacting the pocket well region, and having the first conductivity type, and a metal silicide layer formed in the first region and contacting the source region and the pocket well junction region.
摘要翻译：非易失性存储器件包括限定半导体衬底中的有源区的器件隔离膜，形成在有源区的上部并具有第一导电类型的凹穴阱区，形成在有源区上并延伸到相交的栅电极有源区，隧道绝缘膜，电荷存储膜和顺序地设置在有源区和栅电极之间的阻挡绝缘膜，分别形成在有源区和栅极的第一区和第二区中的源区和漏区在所述栅电极的两侧露出，并且具有与所述第一导电类型相反的第二导电类型的凹穴结区，形成在与所述源极区相邻的所述第一区域中并且与所述凹穴阱区接触并且具有第一导电型，以及形成在第一区域中的金属硅化物层，并且与源极区域和凹穴阱结区域接触。

2. 发明申请

US20100252894A1 Memory devices having diodes and methods of fabricating the same 有权
标题翻译：具有二极管的存储器件及其制造方法
公开(公告)号：US20100252894A1
公开(公告)日：2010-10-07
申请号：US12661117
申请日：2010-03-11
申请人： Byung Sup Shim
发明人： Byung Sup Shim
IPC分类号： H01L27/115 , H01L27/06
CPC分类号： H01L27/11517 , H01L27/0255 , H01L27/115
摘要： A non-volatile memory devices includes: a substrate including a circuit device and a metal line electrically connected with the circuit device; a diode connected with the metal line in a vertical direction with respect to a surface of the substrate, and including a metal layer disposed on a lower part of the diode facing the surface of the substrate; and a resistor electrically connected with the diode in series.
摘要翻译：非易失性存储器件包括：衬底，包括电路器件和与电路器件电连接的金属线; 与金属线相对于衬底的表面在垂直方向上连接的二极管，并且包括设置在面向衬底表面的二极管的下部上的金属层; 以及与二极管串联电连接的电阻器。

3. 发明申请

US20100197109A1 METHOD OF FORMING ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件隔离结构的方法
公开(公告)号：US20100197109A1
公开(公告)日：2010-08-05
申请号：US12639035
申请日：2009-12-16
申请人： YONG-SIK JEONG , JEONG-UK HAN , WEON-HO PARK , BYUNG-SUP SHIM
发明人： YONG-SIK JEONG , JEONG-UK HAN , WEON-HO PARK , BYUNG-SUP SHIM
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L21/76229
摘要： Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed.
摘要翻译：提供了一种形成半导体器件的隔离结构的方法，该半导体器件能够最小化执行图案化处理的次数并具有各种深度的沟槽。该方法包括使用第一图案化工艺部分蚀刻半导体衬底以形成具有第一深度的第一沟槽和第二沟槽。半导体衬底具有第一至第三区域。第一沟槽形成在第一区域中，第二沟槽形成在第二区域中。使用第二图案化工艺部分地蚀刻半导体衬底，使得第三沟槽形成在第三区域中，并且第四沟槽形成在第二区域中。第四个沟槽从第二个沟槽的底部延伸。第三沟槽具有第二深度，第四沟槽具有第三深度。形成了填充第一至第四沟槽的隔离层。

4. 发明授权

US08318583B2 Method of forming isolation structure of semiconductor device 有权
标题翻译：形成半导体器件隔离结构的方法
公开(公告)号：US08318583B2
公开(公告)日：2012-11-27
申请号：US12639035
申请日：2009-12-16
申请人： Yong-Sik Jeong , Jeong-Uk Han , Weon-Ho Park , Byung-Sup Shim
发明人： Yong-Sik Jeong , Jeong-Uk Han , Weon-Ho Park , Byung-Sup Shim
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed.
摘要翻译：提供了一种形成半导体器件的隔离结构的方法，该半导体器件能够最小化执行图案化处理的次数并具有各种深度的沟槽。该方法包括使用第一图案化工艺部分蚀刻半导体衬底以形成具有第一深度的第一沟槽和第二沟槽。半导体衬底具有第一至第三区域。第一沟槽形成在第一区域中，第二沟槽形成在第二区域中。使用第二图案化工艺部分地蚀刻半导体衬底，使得第三沟槽形成在第三区域中，并且第四沟槽形成在第二区域中。第四个沟槽从第二个沟槽的底部延伸。第三沟槽具有第二深度，第四沟槽具有第三深度。形成了填充第一至第四沟槽的隔离层。

5. 发明申请

US20120070949A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及半导体器件制造方法
公开(公告)号：US20120070949A1
公开(公告)日：2012-03-22
申请号：US13180613
申请日：2011-07-12
申请人： Tea-Kwang Yu , Byung-Sup Shim , Yong-Kyu Lee , Bo-Young Seo , Yong-Tae Kim
发明人： Tea-Kwang Yu , Byung-Sup Shim , Yong-Kyu Lee , Bo-Young Seo , Yong-Tae Kim
IPC分类号： H01L21/8239 , H01L21/8229
CPC分类号： H01L27/2436 , H01L27/105 , H01L27/2445 , H01L45/1683
摘要： A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.
摘要翻译：一种制造半导体器件的方法包括提供具有存储块和在其中定义的逻辑块的衬底，在存储块上形成伪栅极图案; 在伪栅极图案的一侧形成第一导电类型的第一区域和在虚拟栅极图案的另一侧形成第二导电类型的第二区域，以及形成与第一区域电连接的非易失性存储器件。

6. 发明授权

US08476130B2 Semiconductor device and method of fabricating semiconductor device 有权
标题翻译：半导体器件及半导体器件的制造方法
公开(公告)号：US08476130B2
公开(公告)日：2013-07-02
申请号：US13180613
申请日：2011-07-12
申请人： Tea-Kwang Yu , Byung-Sup Shim , Yong-Kyu Lee , Bo-Young Seo , Yong-Tae Kim
发明人： Tea-Kwang Yu , Byung-Sup Shim , Yong-Kyu Lee , Bo-Young Seo , Yong-Tae Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/2436 , H01L27/105 , H01L27/2445 , H01L45/1683
摘要： A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.
摘要翻译：一种制造半导体器件的方法包括提供具有存储块和在其中定义的逻辑块的衬底，在存储块上形成伪栅极图案; 在伪栅极图案的一侧形成第一导电类型的第一区域和在虚拟栅极图案的另一侧形成第二导电类型的第二区域，以及形成与第一区域电连接的非易失性存储器件。

7. 发明授权

US08115258B2 Memory devices having diodes and resistors electrically connected in series 有权
标题翻译：具有二极管和电阻串联电连接的存储器件
公开(公告)号：US08115258B2
公开(公告)日：2012-02-14
申请号：US12661117
申请日：2010-03-11
申请人： Byung Sup Shim
发明人： Byung Sup Shim
IPC分类号： H01L29/861
CPC分类号： H01L27/11517 , H01L27/0255 , H01L27/115
摘要： A non-volatile memory devices includes: a substrate including a circuit device and a metal line electrically connected with the circuit device; a diode connected with the metal line in a vertical direction with respect to a surface of the substrate, and including a metal layer disposed on a lower part of the diode facing the surface of the substrate; and a resistor electrically connected with the diode in series.
摘要翻译：非易失性存储器件包括：衬底，包括电路器件和与电路器件电连接的金属线; 与金属线相对于衬底的表面在垂直方向上连接的二极管，并且包括设置在面向衬底表面的二极管的下部上的金属层; 以及与二极管串联电连接的电阻器。

8. 发明申请

US20050124119A1 Open drain input/output structure and manufacturing method thereof in semiconductor device 审中-公开
标题翻译：半导体器件中的开漏输入/输出结构及其制造方法
公开(公告)号：US20050124119A1
公开(公告)日：2005-06-09
申请号：US11039970
申请日：2005-01-20
申请人： Byung-Sup Shim , Young-Ho Kim
发明人： Byung-Sup Shim , Young-Ho Kim
IPC分类号： H01L27/102 , H01L21/8234 , H01L27/088 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/1045
摘要： The present invention relates to an open drain input/output structure and manufacturing method thereof in which a n-channel depletion transistor for pull-up resistance can be used like an enhancement transistor without impurity ion implantation process when being formed an open drain input/output terminal. An open drain input/output structure in a semiconductor device according to the present invention includes: a gate formed with an enhancement transistor at a predetermined portion on a first conductive-type semiconductor substrate which is formed with a gate insulating layer; a second conductive-type source/drain region formed in the semiconductor substrate at the both sides of the gate; and a second conductive-type impurity implantation region formed at a predetermined portion of a channel region at the lower part of the gate so as to selectively connected to the source region or the drain region. Therefore, according to the present invention, because the gate length of a n-channel depletion transistor is designed to have longer than conventional ones' so as to changed a depletion transistor into an enhancement transistor there is no necessary an impurity ion implantation process after gate forming process when an open drain I/O is achieved. Therefore, all a pull-up resistance I/O and an open drain I/O of a mask ROM embedded MCU, EPROM embedded MCU can be achieved with the same lay out structure thereby to be compatible when being manufactured MCU.
摘要翻译：本发明涉及一种开漏输入/输出结构及其制造方法，其中当形成开漏输入/输出时，可以使用上拉电阻的n沟道耗尽晶体管，像无杂质离子注入工艺的增强型晶体管终奌站。根据本发明的半导体器件中的开漏输入/输出结构包括：在第一导电型半导体衬底上的预定部分形成有形成有栅极绝缘层的增强晶体管的栅极; 形成在栅极两侧的半导体衬底中的第二导电型源/漏区; 以及形成在栅极的下部的沟道区的预定部分处以选择性地连接到源极区或漏极区的第二导电型杂质注入区。因此，根据本发明，由于n沟道耗尽晶体管的栅极长度被设计成比常规栅极长，因此将耗尽晶体管改变为增强晶体管，栅极之后不需要杂质离子注入工艺当达到开漏I / O时，形成工艺。因此，所有上拉电阻I / O和掩模ROM嵌入式MCU的开漏I / O，EPROM嵌入式MCU都可以通过相同的布局结构实现，从而在制造MCU时兼容。

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