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1. 发明申请

US20150052293A1 HIDDEN CORE TO FETCH DATA 审中-公开
标题翻译：隐藏核心到FETCH数据
公开(公告)号：US20150052293A1
公开(公告)日：2015-02-19
申请号：US14387598
申请日：2012-04-30
申请人： Blaine D. Gaither , Russ W. Herrell , Craig Warner
发明人： Blaine D. Gaither , Russ W. Herrell , Craig Warner
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0808 , G06F12/0831 , G06F2212/507 , G06F2212/602 , G06F2212/621 , G06F2212/7201
摘要： A computing device includes a home node controller to couple a home processor socket to the computing device. The home processor socket includes a home core hidden from the computing device and the home core fetches data to a home cache of the home processor socket. The computing device includes a source processor socket including a source core to request for data and the home node controller forwards requested data from the home cache to the source core if the requested data is included on the home cache.
摘要翻译：计算设备包括将家庭处理器插座耦合到计算设备的家庭节点控制器。家庭处理器插座包括从计算设备隐藏的本地核心，并且本地核心将数据提取到家庭处理器插座的家庭缓存。计算设备包括源处理器插座，其包括用于请求数据的源核心，并且如果所请求的数据被包括在家用高速缓存中，则家庭节点控制器将所请求的数据从家庭高速缓存转发到源核心。

2. 发明申请

US20090037162A1 DATACENTER WORKLOAD MIGRATION 审中-公开
公开(公告)号：US20090037162A1
公开(公告)日：2009-02-05
申请号：US11831541
申请日：2007-07-31
申请人： Blaine D. Gaither , Russ W. Herrell
发明人： Blaine D. Gaither , Russ W. Herrell
IPC分类号： G06F17/50
CPC分类号： G06F1/3203
摘要： A method is provided for evaluating workload migration from a target computer in a datacenter. The method includes tracking the number of power cycles occurring for a plurality of computers located within the datacenter and generating power cycling information as a result of the tracking. The method further includes determining whether to power cycle the target computer based on the power cycling information.
摘要翻译：提供了一种方法，用于评估数据中心中目标计算机的工作负载迁移。该方法包括跟踪位于数据中心内的多个计算机发生的功率周期数，并且作为跟踪的结果产生功率循环信息。该方法还包括基于功率循环信息确定是否对目标计算机进行重新开机。

3. 发明授权

US06574710B1 Computer cache system with deferred invalidation 失效
标题翻译：具有延迟无效的计算机缓存系统
公开(公告)号：US06574710B1
公开(公告)日：2003-06-03
申请号：US09629128
申请日：2000-07-31
申请人： Blaine D. Gaither , Russ W Herrell
发明人： Blaine D. Gaither , Russ W Herrell
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0831
摘要： A lower level cache detects when a line of memory has been evicted from a higher level cache. The lower level cache stores the address of the evicted line. When the system bus is idle, the lower level cache initiates a transaction causing all higher level caches to invalidate the line. The lower level cache then places the line into a special state. If a line in the special state is evicted from the lower level cache, the lower level cache knows that the line is not cached at a higher level, and therefore a back-invalidate transaction is not needed.
摘要翻译：较低级别的缓存检测何时一行内存已从较高级别的缓存中逐出。下级缓存存储被驱逐行的地址。当系统总线空闲时，较低级别的缓存启动一个事务，导致所有较高级别的缓存使该行无效。然后，较低级别的缓存将该行置于特殊状态。如果特殊状态的行从较低级缓存中逐出，则较低级别的缓存知道该行不会在较高级别缓存，因此不需要后退无效事务。

4. 发明申请

US20120311267A1 EXTERNAL CACHE OPERATION BASED ON CLEAN CASTOUT MESSAGES 有权
标题翻译：基于清除CASTOUT消息的外部缓存操作
公开(公告)号：US20120311267A1
公开(公告)日：2012-12-06
申请号：US13149493
申请日：2011-05-31
申请人： Blaine D. Gaither , David A. Plettner
发明人： Blaine D. Gaither , David A. Plettner
IPC分类号： G06F12/08
CPC分类号： G06F12/128 , G06F12/0802 , G06F12/12
摘要： A processor transmits clean castout messages indicating that a cache line is not dirty and is no longer being stored by a lowest level cache of the processor. An external cache receives the clean castout messages and manages cache lines based in part on the clean castout messages.
摘要翻译：一个处理器传输清除的丢弃消息，指示高速缓存行不脏，并且不再由处理器的最低级缓存存储。外部缓存部分地基于干净的丢弃消息来接收干净的丢弃消息并管理高速缓存行。

5. 发明授权

US08176293B2 Method and system for moving active virtual partitions between computers 有权
标题翻译：在计算机之间移动主动虚拟分区的方法和系统
公开(公告)号：US08176293B2
公开(公告)日：2012-05-08
申请号：US12383766
申请日：2009-03-27
申请人： Blaine D. Gaither , John A. Morrison
发明人： Blaine D. Gaither , John A. Morrison
IPC分类号： G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34 , G06F9/455
CPC分类号： G06F9/4856 , G06F9/45558 , G06F2009/4557
摘要： Embodiments of the present invention are directed to enhancing VPAR monitors to allow an active VPAR to be moved from one machine to another, as well as to enhancing virtual-machine monitors to move active VPARs from one machine to another. Because traditional VPAR monitors lack access to many computational resources and to executing-operating-system state, VPAR movement is carried out primarily by specialized routines executing within active VPARs, unlike the movement of guest operating systems between machines carried out by virtual-machine-monitor routines.
摘要翻译：本发明的实施例涉及增强VPAR监视器以允许主动VPAR从一个机器移动到另一个机器，以及增强虚拟机监视器以将活动VPAR从一个机器移动到另一个机器。由于传统的VPAR监视器无法访问许多计算资源和执行操作系统状态，VPAR运动主要是通过在主动VPAR内执行的专门程序进行的，这与虚拟机监视器执行的机器之间的客户操作系统的移动不同例程。

6. 发明申请

US20100235562A1 SWITCH MODULE BASED NON-VOLATILE MEMORY IN A SERVER 有权
标题翻译：在服务器中基于开关模块的非易失性存储器
公开(公告)号：US20100235562A1
公开(公告)日：2010-09-16
申请号：US12403712
申请日：2009-03-13
申请人： Blaine D. Gaither , Andrew R. Wheeler
发明人： Blaine D. Gaither , Andrew R. Wheeler
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A switch module having shared memory that is allocated to other blade servers. A memory controller partitions and enables access to partitions of the shared memory by requesting blade servers.
摘要翻译：具有分配给其他刀片服务器的共享存储器的交换机模块。内存控制器通过请求刀片服务器来分区并启用对共享内存分区的访问。

7. 发明申请

US20090210628A1 Computer Cache System With Stratified Replacement 有权
标题翻译：具有分层替换的计算机缓存系统
公开(公告)号：US20090210628A1
公开(公告)日：2009-08-20
申请号：US12194687
申请日：2008-08-20
申请人： Blaine D. Gaither
发明人： Blaine D. Gaither
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/082 , G06F12/128
摘要： Methods for selecting a line to evict from a data storage system are provided. A computer system implementing a method for selecting a line to evict from a data storage system is also provided. The methods include selecting an uncached class line for eviction prior to selecting a cached class line for eviction.
摘要翻译：提供了从数据存储系统中选择要排除的行的方法。还提供了一种实现用于从数据存储系统中选择要排出的行的方法的计算机系统。这些方法包括在选择一个缓存的等级线进行驱逐之前，选择一个未被缓存的类别线。

8. 发明申请

US20080104329A1 CACHE AND METHOD FOR CACHE BYPASS FUNCTIONALITY 有权
标题翻译：用于缓存旁路功能的缓存和方法
公开(公告)号：US20080104329A1
公开(公告)日：2008-05-01
申请号：US11554827
申请日：2006-10-31
申请人： Blaine D. Gaither , Patrick Knebel
发明人： Blaine D. Gaither , Patrick Knebel
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0804 , G06F12/0815 , G06F12/0897
摘要： A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.
摘要翻译：提供了用于将处理器与主存储器可操作地耦合的高速缓存。高速缓存包括与高速缓冲存储器可操作地耦合的高速缓冲存储器和高速缓存控制器。缓存控制器被配置为接收由高速缓冲存储器或主存储器满足的存储器请求。此外，高速缓存控制器被配置为处理高速缓存活动信息以使至少一个存储器请求绕过高速缓冲存储器。

9. 发明授权

US06889244B1 Method and apparatus for passing messages using a fault tolerant storage system 有权
标题翻译：使用容错存储系统传递消息的方法和装置
公开(公告)号：US06889244B1
公开(公告)日：2005-05-03
申请号：US09703427
申请日：2000-10-31
申请人： Blaine D. Gaither , Bret A. McKee
发明人： Blaine D. Gaither , Bret A. McKee
IPC分类号： G06F15/16 , H04L29/08
CPC分类号： H04L67/1097 , G06F9/54 , H04L67/303
摘要： A method and apparatus pass messages between server and client applications using a fault tolerant storage system (FTSS). The interconnection fabric that couples the FTSS to the computer systems that host the client and server applications may also be used to carry messages. A networked system capable of hosting a distributed application includes a plurality of computer systems coupled to an FTSS via an FTSS interconnection fabric. The FTSS not only processes file-related I/O transactions, but also includes several message agents to facilitate message transfer in a reliable and fault tolerant manner. The message agents include a conversational communication agent, an event-based communication agent, a queue-based communication agent, a request/reply communication agent, and an unsolicited communication agent. The highly reliable and fault tolerant nature of the FTSS ensures that the FTSS can guarantee delivery of a message transmitted from a sending computer system to a destination computer system. As soon as a message is received by the FTSS from a sending computer system, the message is committed to a nonvolatile fault tolerant write cache. Thereafter, the message is written to a redundant array of independent disks (RAID) of the FTSS, and processed by one of the message agents.
摘要翻译：一种方法和设备使用容错存储系统（FTSS）在服务器和客户端应用程序之间传递消息。将FTSS耦合到托管客户端和服务器应用程序的计算机系统的互连结构也可以用于携带消息。能够托管分布式应用的联网系统包括经由FTSS互连结构耦合到FTSS的多个计算机系统。 FTSS不仅处理文件相关的I / O事务，还包括几个消息代理，以便以可靠和容错的方式促进消息传输。消息代理包括会话通信代理，基于事件的通信代理，基于队列的通信代理，请求/应答通信代理和未经请求的通信代理。 FTSS的高度可靠和容错的性质确保了FTSS可以保证从发送计算机系统传送到目标计算机系统的消息的传送。一旦FTSS从发送计算机系统接收到消息，该消息被提交到非易失性容错写缓存。此后，消息被写入FTSS的独立磁盘（RAID）的冗余阵列，并由消息代理之一处理。

10. 发明授权

US06813691B2 Computer performance improvement by adjusting a count used for preemptive eviction of cache entries 失效
标题翻译：通过调整用于抢先驱逐缓存条目的计数来提高计算机性能
公开(公告)号：US06813691B2
公开(公告)日：2004-11-02
申请号：US10001584
申请日：2001-10-31
申请人： Blaine D. Gaither , Benjamin D. Osecky
发明人： Blaine D. Gaither , Benjamin D. Osecky
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0831 , G06F12/0897 , Y10S707/99932
摘要： A cache system improves performance by limiting the number of dirty entries in a cache. The cache system may be further improve performance by limiting the number of dirty entries in a cache that might be subject to a cache-to-cache transfer. In a first example, a cache system counts the total number of dirty entries in the cache and preemptively evicts at least one dirty entry when the count exceeds a predetermined threshold. In a variation, a cache system counts dirty cache entries that result from a cache-to-cache transfer, and evicts at least one dirty entry that results from a cache-to-cache transfer when the number exceeds a predetermined threshold. For either system, the predetermined threshold may be dynamically varied to determine a value that optimizes performance.
摘要翻译：缓存系统通过限制高速缓存中脏条目的数量来提高性能。缓存系统可以通过限制高速缓存中可能受到高速缓存到高速缓存传输的脏条目的数量来进一步提高性能。在第一示例中，高速缓存系统对高速缓存中的脏条目的总数进行计数，并且当计数超过预定阈值时，预先将至少一个脏条目排除。在一个变型中，缓存系统计算由高速缓存到高速缓存传输所产生的脏缓存条目，并且当数量超过预定阈值时，将至少一个由高速缓存到高速缓存传输产生的脏条目驱逐出去。对于任一系统，可以动态地改变预定阈值以确定优化性能的值。

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