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    • 3. 发明授权
    • System and method for recovery from address errors
    • 从地址错误中恢复的系统和方法
    • US06405322B1
    • 2002-06-11
    • US09290942
    • 1999-04-13
    • Blaine D. GaitherJohn A. MorrisonJohn R. Feehrer
    • Blaine D. GaitherJohn A. MorrisonJohn R. Feehrer
    • G06F1216
    • G06F12/0831G06F11/004G06F11/0724G06F11/073G06F11/0793G06F11/0796
    • A device and method for recovery from address errors is described. When an address error is detected on a local channel, such as a local bus, the coherency states of one or more lines of cache memory associated with the local channel are read, and actions are taken in response. Reading of coherency states ranges from a complete and active interrogation of all cache lines, to a selective and passive interrogation, such as in responding to snoop requests. If the data state consistency is unknown, such as when the MESI state is Modified (M) or Exclusive (E), then the corresponding data in main memory is poisoned. Poisoning may be accomplished by writing a detectable but unrecoverable error pattern in the main memory. Alternatively, the same effect may be accomplished by signaling a hard error on the system bus. If the data state consistency of an interrogated cache line is Shared (S) or Invalid (I), the line may be ignored or the line marked invalid. If the state of the cached line is valid and consistent, such as the “Modified uncached” (Mu) state in a MuMESI protocol, then the line may be written to main memory or provided to a snoop requester.
    • 描述用于从地址错误中恢复的设备和方法。 当在本地信道(例如本地总线)上检测到地址错误时,读取与本地信道相关联的一行或多行高速缓冲存储器的一致性状态,并作出响应。 相关性状态的读取范围从所有高速缓存行的完整和主动询问,到选择性和被动询问,例如响应窥探请求。 如果数据状态一致性未知,例如当MESI状态为M(M)或Exclusive(E)时,则主存储器中的相应数据中毒。 中毒可以通过在主存储器中写入可检测但不可恢复的错误模式来实现。 或者,通过在系统总线上发出硬错误来实现相同的效果。 如果询问的高速缓存行的数据状态一致性为Shared(S)或Invalid(I),则该行可能会被忽略或标记为无效的行。 如果缓存行的状态是有效且一致的,例如MuMESI协议中的“Modified uncached”(Mu)状态,则该行可以写入主存储器或提供给窥探请求者。
    • 7. 发明授权
    • Allocating resources to partitions in a partitionable computer
    • 将资源分配到可分区计算机中的分区
    • US07606995B2
    • 2009-10-20
    • US10898590
    • 2004-07-23
    • Russ HerrellGerald J. Kaufman, Jr.John A. Morrison
    • Russ HerrellGerald J. Kaufman, Jr.John A. Morrison
    • G06F15/00
    • G06F9/5077
    • Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies the first partition. The first partition identification value is stored in the first physical address to produce a partition-identifying address, which may be transmitted to a system fabric. In another embodiment, a transaction is received which includes a source terminus identifier identifying a source device which transmitted the transaction. It is determined, based on the source terminus identifier, whether the source device is allocated to the same partition as any of the plurality of resources. If the source device is so allocated, the transaction is transmitted to a resource that is allocated to the same partition as the source device.
    • 提供了用于在芯片上分配多个资源到可分区计算机系统中的多个分区的技术。 在一个实施例中,分配给第一分区的资源在分配给第一分区的地址空间中生成物理地址。 分区标识值标识第一个分区。 第一分区识别值被存储在第一物理地址中以产生可以被发送到系统结构的分区识别地址。 在另一个实施例中,接收到交易,其包括标识发送交易的源设备的源终端标识符。 基于源终端标识符确定源设备是否被分配给与多个资源中的任一个相同的分区。 如果源设备如此分配,则将事务发送到分配给与源设备相同的分区的资源。
    • 10. 发明授权
    • Apparatus and method for converting interrupt transactions to interrupt signals to distribute interrupts to IA-32 processors
    • 将中断事务转换为中断信号以将中断分配给IA-32处理器的装置和方法
    • US06625679B1
    • 2003-09-23
    • US09294927
    • 1999-04-19
    • John A. MorrisonMichael S. AllisonLeo J. Embry
    • John A. MorrisonMichael S. AllisonLeo J. Embry
    • G06F1324
    • G06F13/4022
    • An apparatus and method for distributing interrupts to Intel® Architecture (IA)-32 processors includes a system bus having a number of nodes. Each node includes a bridge that couples the system bus to a processor bus. The processor bus may include multiple IA-32 processors. The system bus may include any number of nodes. Interrupt transactions appearing on the system bus are converted by the bridge to interrupt signals. The bridge asserts the interrupt signals at one of two pins on a target IA-32 processor. One pin may be programmed to receive non-maskable interrupts and the other pin may be programmed to receive external interrupts. The bridge incorporates a priority and threshold mechanism. The bridge includes a buffer to store pending interrupt signals. The apparatus and method may be used in a mixed IA-32 and IA-64 computer architecture that uses IA-64 components to receive interrupts and uses the bridge to convert the transactions on an IA-64 bus into interrupt signal assertions to an IA-32 processor.
    • 用于向Intel(R)架构(IA)-32处理器分配中断的装置和方法包括具有多个节点的系统总线。 每个节点包括将系统总线耦合到处理器总线的桥。 处理器总线可以包括多个IA-32处理器。 系统总线可以包括任何数量的节点。 系统总线上出现的中断事务由桥转换为中断信号。 桥接器将目标IA-32处理器的两个引脚之一置为中断信号。 一个引脚可能被编程为接收不可屏蔽的中断,另一个引脚可能被编程为接收外部中断。 桥梁结合了优先级和阈值机制。 该桥包括一个用于存储未决中断信号的缓冲器。 该装置和方法可以在使用IA-64组件接收中断的混合IA-32和IA-64计算机体系结构中使用,并使用该桥将IA-64总线上的事务转换为IA- 32处理器。