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1. 发明申请

US20130125100A1 COMPUTER SYSTEM AND METHOD FOR COMPILING PROGRAM CODE AND ASSIGNING ADDRESS SPACES 审中-公开
标题翻译：用于编译程序代码和计算地址空间的计算机系统和方法
公开(公告)号：US20130125100A1
公开(公告)日：2013-05-16
申请号：US13296967
申请日：2011-11-15
申请人： Bixia Zheng , Benedict R. Gaster , Dz-Ching Ju
发明人： Bixia Zheng , Benedict R. Gaster , Dz-Ching Ju
IPC分类号： G06F9/45
CPC分类号： G06F8/427
摘要： A computer system is provided for compiling program code and a method for compiling program code by a processor. The method, for example, includes, but is not limited to, receiving, by the processor, the program code and compiling, by the processor, the program code, wherein the processor, when compiling the program code, parses the program code and assigns a default address space qualifier to each member functions without a defined address space qualifier and, when the member function is used, infers an address space for each default address qualifier based upon how the respective member function is being used.
摘要翻译：提供用于编译程序代码的计算机系统和用于由处理器编译程序代码的方法。该方法例如包括但不限于由处理器接收程序代码并由处理器编译程序代码，其中处理器在编译程序代码时解析程序代码并分配每个成员函数的默认地址空间限定符，而没有定义的地址空间限定符，并且当使用成员函数时，基于如何使用相应的成员函数推测每个默认地址限定符的地址空间。

2. 发明授权

US08683468B2 Automatic kernel migration for heterogeneous cores 有权
标题翻译：异构核心的自动内核迁移
公开(公告)号：US08683468B2
公开(公告)日：2014-03-25
申请号：US13108438
申请日：2011-05-16
申请人： Mauricio Breternitz , Patryk Kaminski , Keith Lowery , Anton Chernoff , Dz-Ching Ju
发明人： Mauricio Breternitz , Patryk Kaminski , Keith Lowery , Anton Chernoff , Dz-Ching Ju
IPC分类号： G06F9/46
CPC分类号： G06F9/4856 , G06F9/5066
摘要： A system and method for automatically migrating the execution of work units between multiple heterogeneous cores. A computing system includes a first processor core with a single instruction multiple data micro-architecture and a second processor core with a general-purpose micro-architecture. A compiler predicts execution of a function call in a program migrates at a given location to a different processor core. The compiler creates a data structure to support moving live values associated with the execution of the function call at the given location. An operating system (OS) scheduler schedules at least code before the given location in program order to the first processor core. In response to receiving an indication that a condition for migration is satisfied, the OS scheduler moves the live values to a location indicated by the data structure for access by the second processor core and schedules code after the given location to the second processor core.
摘要翻译：一种用于在多个异构核心之间自动迁移工作单元执行的系统和方法。计算系统包括具有单指令多数据微架构的第一处理器核心和具有通用微架构的第二处理器核心。编译器预测程序中的函数调用的执行在给定位置迁移到不同的处理器核心。编译器创建一个数据结构，以支持在给定位置移动与执行函数调用相关联的实时值。操作系统（OS）调度器将程序顺序之前的给定位置之前的至少代码调度到第一处理器核心。响应于接收到满足迁移条件的指示，OS调度器将活动值移动到由数据结构指示的位置，以供第二处理器核心访问，并且将给定位置之后的代码调度到第二处理器核心。

3. 发明申请

US20050149918A1 Inter-procedural allocation of stacked registers for a processor 有权
标题翻译：用于处理器的堆叠寄存器的程序间分配
公开(公告)号：US20050149918A1
公开(公告)日：2005-07-07
申请号：US10747426
申请日：2003-12-29
申请人： Yang Liu , Sun Chan , Guangrong Gao , Dz-Ching Ju , Guei-Yuan Lueh , Zhaoqing Zhang
发明人： Yang Liu , Sun Chan , Guangrong Gao , Dz-Ching Ju , Guei-Yuan Lueh , Zhaoqing Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： A method for an allocation of stacked registers for Intel's Itanium® processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.
摘要翻译：英特尔安腾（R）处理器分配堆叠寄存器的方法包括三步骤过程。步骤I通过具有多个过程的程序来确定程序内堆叠的寄存器使用。在步骤II中，所公开的方法执行程序间分析以将堆叠的寄存器使用的配额分配给每个过程。在步骤III中，基于步骤II的配额分配，分配每个过程的堆叠寄存器使用。

4. 发明申请

US20120297163A1 AUTOMATIC KERNEL MIGRATION FOR HETEROGENEOUS CORES 有权
标题翻译：自动KERNEL移动异构牙
公开(公告)号：US20120297163A1
公开(公告)日：2012-11-22
申请号：US13108438
申请日：2011-05-16
申请人： Mauricio Breternitz , Patryk Kaminski , Keith Lowery , Anton Chernoff , Dz-Ching Ju
发明人： Mauricio Breternitz , Patryk Kaminski , Keith Lowery , Anton Chernoff , Dz-Ching Ju
IPC分类号： G06F9/315 , G06F15/80
CPC分类号： G06F9/4856 , G06F9/5066
摘要： A system and method for automatically migrating the execution of work units between multiple heterogeneous cores. A computing system includes a first processor core with a single instruction multiple data micro-architecture and a second processor core with a general-purpose micro-architecture. A compiler predicts execution of a function call in a program migrates at a given location to a different processor core. The compiler creates a data structure to support moving live values associated with the execution of the function call at the given location. An operating system (OS) scheduler schedules at least code before the given location in program order to the first processor core. In response to receiving an indication that a condition for migration is satisfied, the OS scheduler moves the live values to a location indicated by the data structure for access by the second processor core and schedules code after the given location to the second processor core.
摘要翻译：一种用于在多个异构核心之间自动迁移工作单元执行的系统和方法。计算系统包括具有单指令多数据微架构的第一处理器核心和具有通用微架构的第二处理器核心。编译器预测程序中的函数调用的执行在给定位置迁移到不同的处理器核心。编译器创建一个数据结构，以支持在给定位置移动与执行函数调用相关联的实时值。操作系统（OS）调度器将程序顺序之前的给定位置之前的至少代码调度到第一处理器核心。响应于接收到满足迁移条件的指示，OS调度器将活动值移动到由数据结构指示的位置，以供第二处理器核心访问，并且将给定位置之后的代码调度到第二处理器核心。

5. 发明申请

US20070226720A1 System and Method for Efficiently Passing Information Between Compiler and Post-Compile-Time Software 审中-公开
标题翻译：在编译器和后期编译软件之间有效传递信息的系统和方法
公开(公告)号：US20070226720A1
公开(公告)日：2007-09-27
申请号：US11756228
申请日：2007-05-31
申请人： Ding-Kai Chen , Dz-Ching Ju
发明人： Ding-Kai Chen , Dz-Ching Ju
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/441 , G06F9/30076 , G06F9/30145
摘要： System and method are described for register optimization during code translation utilizes a technique that removes the time overhead for analyzing register usage and eliminates fixed restraints on the compiler register usage. The present invention for register optimization utilizes a compiler to produce a register usage bit vector in a NOP instruction within each basic block (i.e., subroutine, function, and/or procedure). Each bit in the bit vector represents a particular caller-saved register. A bit is set if, at the location of NOP instruction, the compiler uses the corresponding register within that basic block containing the NOP instruction to hold information to be used at a later time. During the translation, the translator examines the register usage bit vector to very quickly determine which registers are free and therefore can be used during the register optimization without the need to save and restore the register values.
摘要翻译：在代码转换中描述了用于寄存器优化的系统和方法，该技术消除了分析寄存器使用的时间开销并消除了对编译器寄存器使用的固定约束。用于寄存器优化的本发明利用编译器在每个基本块（即，子程序，功能和/或过程）中的NOP指令中产生寄存器使用位向量。位向量中的每个位表示特定的调用者保存的寄存器。如果在NOP指令的位置，编译器使用包含NOP指令的基本块内的对应寄存器来保存稍后使用的信息，则置位。在翻译期间，翻译器检查寄存器使用位向量，以快速确定哪些寄存器是空闲的，因此可以在寄存器优化期间使用，而不需要保存和恢复寄存器值。

6. 发明授权

US07058937B2 Methods and systems for integrated scheduling and resource management for a compiler 失效
公开(公告)号：US07058937B2
公开(公告)日：2006-06-06
申请号：US10121763
申请日：2002-04-12
申请人： Chen Fu , Dong-Yuan Chen , Chengyong Wu , Dz-Ching Ju
发明人： Chen Fu , Dong-Yuan Chen , Chengyong Wu , Dz-Ching Ju
IPC分类号： G06F9/45
CPC分类号： G06F9/3853 , G06F8/445
摘要： A compiler comprising an integrated instruction scheduler and resource management system is provided. According to an aspect of an embodiment, the resource management system includes a function unit based finite state automata system. Instructions to be compiled are modeled through the function unit based finite state automata system based on their function unit usage, before they are emitted as compiled computer code. We also disclose a function unit based finite state automata data structure and computer implemented methods for making the same.

7. 发明授权

US07082602B2 Function unit based finite state automata data structure, transitions and methods for making the same 失效
公开(公告)号：US07082602B2
公开(公告)日：2006-07-25
申请号：US10121982
申请日：2002-04-12
申请人： Chen Fu , Dong-Yuan Chen , Chengyong Wu , Dz-Ching Ju
发明人： Chen Fu , Dong-Yuan Chen , Chengyong Wu , Dz-Ching Ju
IPC分类号： G06F9/45
CPC分类号： G06F9/3853 , G06F8/445
摘要： We disclose a function unit based finite state automata data structure for use in computer program compilers. According to an aspect of an embodiment, the data structure comprises a function unit vector, having no more used bits than there are issue ports for any particular microprocessor, and a plurality of valid template assignments for each function unit vector. In a preferred embodiment, the template assignments are constructed so as to account for dispersal rules associated with the particular microprocessor. Further, the template assignments can be sorted according to priority data.

8. 发明授权

US07257806B1 System and method for efficiently passing information between compiler and post-compile-time software 失效
标题翻译：在编译器和编译后软件之间有效传递信息的系统和方法
公开(公告)号：US07257806B1
公开(公告)日：2007-08-14
申请号：US09422539
申请日：1999-10-21
申请人： Ding-Kai Chen , Dz-Ching Ju
发明人： Ding-Kai Chen , Dz-Ching Ju
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/441 , G06F9/30076 , G06F9/30145
摘要： System and method are described for register optimization during code translation utilizes a technique that removes the time overhead for analyzing register usage and eliminates fixed restraints on the compiler register usage. The present invention for register optimization utilizes a compiler to produce a register usage bit vector in a NOP instruction within each basic block (i.e., subroutine, function, and/or procedure). Each bit in the bit vector represents a particular caller-saved register. A bit is set if, at the location of NOP instruction, the compiler uses the corresponding register within that basic block containing the NOP instruction to hold information to be used at a later time. During the translation, the translator examines the register usage bit vector to very quickly determine which registers are free and therefore can be used during the register optimization without the need to save and restore the register values.
摘要翻译：在代码转换中描述了用于寄存器优化的系统和方法，该技术消除了分析寄存器使用的时间开销并消除了对编译器寄存器使用的固定约束。用于寄存器优化的本发明利用编译器在每个基本块（即，子程序，功能和/或过程）中的NOP指令中产生寄存器使用位向量。位向量中的每个位表示特定的调用者保存的寄存器。如果在NOP指令的位置，编译器使用包含NOP指令的基本块内的对应寄存器来保存稍后使用的信息，则置位。在翻译期间，翻译器检查寄存器使用位向量，以快速确定哪些寄存器是空闲的，因此可以在寄存器优化期间使用，而不需要保存和恢复寄存器值。

9. 发明授权

US06959435B2 Compiler-directed speculative approach to resolve performance-degrading long latency events in an application 失效
标题翻译：编译器指导的推测方法来解决应用程序中降级性能下降的长时间事件
公开(公告)号：US06959435B2
公开(公告)日：2005-10-25
申请号：US09968261
申请日：2001-09-28
申请人： Dz-Ching Ju , Youfeng Wu
发明人： Dz-Ching Ju , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F8/4451
摘要： A compiler-directed speculative approach to resolve performance-degrading long latency events in an application is described. One or more performance-degrading instructions are identified from multiple instructions to be executed in a program. A set of instructions prefetching the performance-degrading instruction is defined within the program. Finally, at least one speculative bit of each instruction of the identified set of instructions is marked to indicate a predetermined execution of the instruction.
摘要翻译：描述了一种以编译器为导向的推测方法来解决应用程序中降级性能下降的长时间事件。从程序中要执行的多个指令来识别一个或多个性能降级指令。在程序中定义预取性能降级指令的一组指令。最后，所标识的指令集的每个指令的至少一个推测位被标记为指示该指令的预定执行。

10. 发明授权

US06898787B2 Method and apparatus for ordered predicate phi in static single assignment form 有权
标题翻译：有序谓词phi的静态单一分配形式的方法和装置
公开(公告)号：US06898787B2
公开(公告)日：2005-05-24
申请号：US09814511
申请日：2001-03-22
申请人： Carol Linda Thompson , Vatsa Santhanam , Dz-Ching Ju , Vasanth Bala
发明人： Carol Linda Thompson , Vatsa Santhanam , Dz-Ching Ju , Vasanth Bala
IPC分类号： G06F9/45
CPC分类号： G06F8/433
摘要： A Φ function provides a mechanism for static single assignment in the presence of predicated code. Guards placed on each source operand of the Φ function indicate the condition under which the corresponding source operand is live and provide correct materialization of the Φ functions after code reordering. For control functions Φc representing a confluence of live reaching definitions at a join point in the control flow graph, the guards indicate the basic block which is the source of the edge associated with the source operand. The Φc operands are paired with the source basic block of the incoming edge(s) along which they are live. The operands are also ordered according to a topological ordering of their associated block. This ordering is maintained through subsequent code transformations. In the topological ordering, the source of the edge from which the definition was passed is defined. A predicate Φ function Φp, represents the confluence of definitions in a straight line of code in which some of the definitions have been predicated. For Φp, the guards on the source operands indicate the predicate under which the corresponding operand is live. The order of the operands is such that the Φp function can be fully materialized by inserting a copy from each source operand to the target variable, in the corresponding order, and each predicated by the associated predicate guard.
摘要翻译： Phi函数提供了在存在预定义代码的情况下进行静态单一分配的机制。在Phi功能的每个源操作数上设置的守卫指示对应的源操作数的实时状态，并在代码重新排序后提供Phi功能的正确实现。对于表示控制流程图中连接点处的实时达成定义的汇合的控制功能，保护指示作为与源操作数相关联的边的源的基本块。 Phi i>>> ands are are are。。。。。。。。。。。。。。。。。。。。。操作数也根据其相关块的拓扑排序进行排序。这种排序通过后续的代码转换来维护。在拓扑排序中定义了通过定义的边缘的源。谓词Phi函数Phi
表示其中某些定义已经被假定的直线代码中的定义的汇合。对于Phi _{p ，源操作数上的守卫表示相应操作数处于活动状态的谓词。操作数的顺序是这样的，通过从相应的顺序将每个源操作数的副本插入到目标变量中，并且每个由相关联的谓词保护者预先定义，可以完全实现Phi}

功能。

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