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    • 2. 发明申请
    • PROGRAMMABLE PHYSICAL ADDRESS MAPPING FOR MEMORY
    • 存储器的可编程物理地址映射
    • US20140082322A1
    • 2014-03-20
    • US13617673
    • 2012-09-14
    • Gabriel H. LohMauricio Breternitz, JR.
    • Gabriel H. LohMauricio Breternitz, JR.
    • G06F12/00
    • G06F12/00G06F12/0207G06F12/0653G06F2212/1016
    • A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.
    • 存储器实现可编程物理地址映射,可以改变以反映对存储器的观察或预期的改变的存储器访问模式。 存储器采用地址解码逻辑,其可以实现物理地址和相应存储器位置之间的各种物理地址映射中的任何一种。 物理地址映射可以将数据定位在存储器的一个或多个存储体和行中,以便于给定访问模式更有效的存储器访问。 存储器的硬件​​采用的可编程物理地址映射可以包括但不限于硬连线逻辑门,可编程查找表或其它映射表,可重构逻辑或其组合。 物理地址映射可以针对整个存储器或基于每存储器区域编程。
    • 4. 发明申请
    • AUTOMATIC LOAD BALANCING FOR HETEROGENEOUS CORES
    • 自动负载平衡异常角
    • US20120291040A1
    • 2012-11-15
    • US13105250
    • 2011-05-11
    • Mauricio BreternitzPatryk KaminskiKeith LoweryAnton Chernoff
    • Mauricio BreternitzPatryk KaminskiKeith LoweryAnton Chernoff
    • G06F9/46
    • G06F9/5083
    • A system and method for efficient automatic scheduling of the execution of work units between multiple heterogeneous processor cores. A processing node includes a first processor core with a general-purpose micro-architecture and a second processor core with a single instruction multiple data micro-architecture. A computer program comprises one or more compute kernels, or function calls. A compiler computes pre-runtime information of the given function call. A runtime scheduler produces one or more work units by matching each of the one or more kernels with an associated record of data. The scheduler assigns work units either to the first or to the second processor core based at least in part on the computed pre-runtime information. In addition, the scheduler is able to change an original assignment for a waiting work unit based on dynamic runtime behavior of other work units corresponding to a same kernel as the waiting work unit.
    • 一种用于在多个异构处理器内核之间高效自动调度工作单元执行的系统和方法。 处理节点包括具有通用微架构的第一处理器核心和具有单个指令多数据微架构的第二处理器核心。 计算机程序包括一个或多个计算内核或函数调用。 编译器计算给定函数调用的运行前信息。 运行时调度器通过将一个或多个内核中的每一个与相关联的数据记录进行匹配来生成一个或多个工作单元。 至少部分地基于所计算的运行前信息,调度器将工作单元分配给第一或第二处理器核。 此外,调度器能够基于与等待工作单元相同的内核的其他工作单元的动态运行时行为来改变等待工作单元的原始分配。
    • 5. 发明授权
    • Method and system for reducing program code size
    • 减少程序代码大小的方法和系统
    • US07725887B2
    • 2010-05-25
    • US11020340
    • 2004-12-22
    • Youfeng WuMauricio Breternitz, Jr.
    • Youfeng WuMauricio Breternitz, Jr.
    • G06F9/45
    • G06F8/4434
    • In a method for reducing code size, replaceable subsets of instructions at first locations in areas of infrequently executed instructions in a set of instructions and target subsets of instructions at second locations in the set of instructions are identified, wherein each replaceable subset matches at least one target subset. If multiple target subsets of instructions match one replaceable subset of instructions, one of the multiple matching target subsets is chosen as the matching target subset for the one replaceable subset based on whether the multiple target subsets are located in regions of frequently executed code. For each of at least some of the replaceable subsets of instructions, the replaceable subset of instructions is replaced with an instruction to cause the matching target subset of instructions at the second location to be executed.
    • 在减少代码大小的方法中,识别在一组指令中的不经常执行的指令的区域中的第一位置处的指令的可替换子集,以及指令集中的第二位置处的目标指令子集,其中每个可替换子集与至少一个 目标子集。 如果指令的多个目标子集匹配一个可替换的指令子集,则基于多个目标子集是否位于经常执行的代码的区域中,将多个匹配目标子集中的一个选择为一个可替换子集的匹配目标子集。 对于至少一些可替换的指令子集中的每一个,可替换的指令子集被替换为使得执行第二位置处的指令的匹配目标子集的指令。
    • 9. 发明授权
    • Method for key escrow in a communication system and apparatus therefor
    • 通信系统中密钥托管的方法及其设备
    • US06823070B1
    • 2004-11-23
    • US09536520
    • 2000-03-28
    • Roger A. SmithMauricio Breternitz, Jr.
    • Roger A. SmithMauricio Breternitz, Jr.
    • H04K100
    • H04L9/0894H04L2209/04
    • Method of monitoring a secure encrypted communication, where the encryption key(s) is recovered by an escrow center having a master and multiple agents and the master receives the key encrypted using a mask scheme. Independent random masks are generated, which are then used to create dependent masks for each agent. The agents receive the mask information but no key information. The agents decide whether to allow the interception of an encrypted message. In response to the agents' decisions, the master is either enabled to recover the key or prevented from recovering the key. Encrypted key information is only available to the master. Multiple combinations of agents will provide sufficient information to the master to recover the key, avoiding the hold-out problems of the prior art. In one embodiment, multiple masters provide back-up protection when a master is unavailable.
    • 监控安全加密通信的方法,其中由具有主代理和多个代理的托管中心恢复加密密钥,并且主机接收使用掩码方案加密的密钥。 生成独立随机掩码,然后用它们为每个代理创建依赖掩码。 代理接收掩码信息,但没有密钥信息。 代理人决定是否允许拦截加密的消息。 响应于代理人的决定,主机可以启用恢复密钥或阻止恢复密钥。 加密的密钥信息仅适用于主服务器。 代理商的多个组合将向主机提供足够的信息以恢复密钥,避免现有技术的保留问题。 在一个实施例中,当主机不可用时,多个主机提供备用保护。
    • 10. 发明授权
    • Data allocation into multiple memories for concurrent access
    • 将数据分配到多个并发访问存储器中
    • US5966143A
    • 1999-10-12
    • US949356
    • 1997-10-14
    • Mauricio Breternitz, Jr.
    • Mauricio Breternitz, Jr.
    • G06F9/45
    • G06F8/441G06F8/443
    • Data is allocated into multiple memories with selective variable replication for maximizing performance by minimizing concurrent memory access conflicts. Requirements for concurrent access are summarized in a transformed concurrent access graph. Graph vertices are merged to disallow variable replication. All potential graph merges that cause a reduction in machine cycle time are identified. The ratios of saved cycles/memory cost in bytes are then computed for each potential merge. The potential merges are then sorted by their saved cycles/bytes ratio. Finally, potential merges resulting in replicated variables are selected based on their cycles/bytes ratios until a predefined memory target size is achieved. Either graph coloring or clique partitioning can be used to allocate variables into memory banks.
    • 数据被分配到具有选择性变量复制的多个存储器中,以通过最小化并发存储器访问冲突来最大化性能。 并发访问的要求在转换的并发访问图中汇总。 图形顶点被合并以禁止变量复制。 确定导致机器周期时间缩短的所有潜在图形合并。 然后为每个潜在的合并计算保存的周期/存储器成本(以字节为单位)的比率。 然后,潜在的合并按照保存的周期/字节比进行排序。 最后,基于它们的周期/字节比率来选择导致复制变量的潜在合并,直到达到预定义的存储器目标大小。 图形着色或集团划分可用于将变量分配到存储体中。