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1. 发明申请

US20070033427A1 Power efficient cycle stealing 审中-公开
标题翻译：有效的循环窃取
公开(公告)号：US20070033427A1
公开(公告)日：2007-02-08
申请号：US11184421
申请日：2005-07-19
申请人： Anthony Correale , Benjamin Bowers , Ying Brown , Veena Pureswaran
发明人： Anthony Correale , Benjamin Bowers , Ying Brown , Veena Pureswaran
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/10
摘要： Arrangements and methods to cycle steal and reduce power consumption in an integrated circuit are disclosed. Embodiments of the invention exploit the art of cycle stealing for increased system performance, while facilitating a more power efficient bypass mode when power conservation is desired over performance. One embodiment includes a network of integrated delay elements employing a multiplexor to transfer either a normal or a delayed clock signal to a clock splitter. Another embodiment includes a network of delay elements, configured to enable or disable power conservation. A further embodiment integrates a configurable delay circuit into a clock splitter arrangement.
摘要翻译：公开了在集成电路中循环窃取和降低功耗的安排和方法。本发明的实施例利用循环窃取的技术来提高系统性能，同时在期望功率节省对性能的同时促进更节能的旁路模式。一个实施例包括采用多路复用器将正常或延迟的时钟信号传送到时钟分离器的集成延迟元件的网络。另一实施例包括被配置为启用或禁用功率节省的延迟元件网络。另一实施例将可配置的延迟电路集成到时钟分配器装置中。

2. 发明申请

US20070101306A1 Methods, systems, and media to improve manufacturability of semiconductor devices 有权
标题翻译：方法，系统和媒体，以提高半导体器件的可制造性
公开(公告)号：US20070101306A1
公开(公告)日：2007-05-03
申请号：US11265641
申请日：2005-11-02
申请人： Benjamin Bowers , Anthony Correale
发明人： Benjamin Bowers , Anthony Correale
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/12 , Y02P90/265
摘要： Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to incorporate the manufacturing improvements. In some embodiments, wires are spread to prevent shorting. In other embodiments, the reliability of contacts and vias is improved by adding additional metallization to the areas surrounding the contacts and vias, or by adding redundant contacts and vias. In one embodiment, a series of manufacturing improvements are made to integrated circuit cells in an iterative fashion.
摘要翻译：公开了用于提高集成电路单元内的单元和结构的可制造性的方法，系统和介质。实施例包括布置可编程单元，布线可编程单元，分析单元布置并互连布线以用于制造改进机会的方法，以及修改可编程单元结构以结合制造改进。在一些实施例中，布线以防止短路。在其他实施例中，通过向周围的触点和通孔附加额外的金属化，或通过添加冗余的触点和通孔来改善触点和通孔的可靠性。在一个实施例中，以迭代方式对集成电路单元进行一系列制造改进。

3. 发明申请

US20080115093A1 SYSTEMS AND MEDIA TO IMPROVE MANUFACTURABILITY OF SEMICONDUCTOR DEVICES 有权
标题翻译：系统和介质提高半导体器件的制造能力
公开(公告)号：US20080115093A1
公开(公告)日：2008-05-15
申请号：US11971171
申请日：2008-01-08
申请人： Benjamin Bowers , Anthony Correale
发明人： Benjamin Bowers , Anthony Correale
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/12 , Y02P90/265
摘要： Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to incorporate the manufacturing improvements. In some embodiments, wires are spread to prevent shorting. In other embodiments, the reliability of contacts and vias is improved by adding additional metallization to the areas surrounding the contacts and vias, or by adding redundant contacts and vias. In one embodiment, a series of manufacturing improvements are made to integrated circuit cells in an iterative fashion.
摘要翻译：公开了用于提高集成电路单元内的单元和结构的可制造性的方法，系统和介质。实施例包括布置可编程单元，布线可编程单元，分析单元布置并互连布线以用于制造改进机会的方法，以及修改可编程单元结构以结合制造改进。在一些实施例中，布线以防止短路。在其他实施例中，通过向周围的触点和通孔附加额外的金属化，或通过添加冗余的触点和通孔来改善触点和通孔的可靠性。在一个实施例中，以迭代方式对集成电路单元进行一系列制造改进。

4. 发明申请

US20070170553A1 Methods and apparatuses for creating integrated circuit capacitance from gate array structures 失效
标题翻译：从门阵列结构产生集成电路电容的方法和装置
公开(公告)号：US20070170553A1
公开(公告)日：2007-07-26
申请号：US11337010
申请日：2006-01-20
申请人： Anthony Correale , Benjamin Bowers , Douglass Lamb , Nishith Rohatgi
发明人： Anthony Correale , Benjamin Bowers , Douglass Lamb , Nishith Rohatgi
IPC分类号： H01L23/62
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/11898 , H01L28/40
摘要： Methods and apparatuses for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise a method of placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
摘要翻译：公开了在集成电路中使用门阵列来形成电容结构的方法和装置。实施例包括将P型场效应晶体管（P-fets）和N型场效应晶体管（N-fets）的栅极阵列放置在集成电路设计中的方法，将一个或多个P-fets的漏极和源极以及用于一个或多个N-fets的门到电源地，以及将一个或多个P-fets的栅极和用于一个或多个N-fets的漏极和源耦合到电源的正电压。在一些实施例中，通过将一个或多个P-fets和一个或多个N-fets分别偏置到正电压和地电位，P-fets和N-fets的电容式设备的源极到漏极泄漏电流被最小化。在其他实施例中，可以使用可熔元件实现电容结构，以在短路的情况下隔离电容结构。

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