专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06798275B1 Fast, accurate and low power supply voltage booster using A/D converter 有权
标题翻译：使用A / D转换器的快速，准确和低电源电压升压器
公开(公告)号：US06798275B1
公开(公告)日：2004-09-28
申请号：US10406415
申请日：2003-04-03
申请人： Binh Quang Le , Cathy Thuvan Ly , Lee Cleveland , Pau-Ling Chen
发明人： Binh Quang Le , Cathy Thuvan Ly , Lee Cleveland , Pau-Ling Chen
IPC分类号： G05F110
CPC分类号： G11C5/145 , G11C8/08
摘要： Flash memory array systems and methods are disclosed for producing a regulated boosted word line voltage for read operations. The system comprises a multi-stage voltage boost circuit operable to receive a supply voltage and one or more output signals from a supply voltage detection circuit to generate the boosted word line voltage having a value greater than the supply voltage. The voltage boost circuit comprises a precharge circuit and a plurality of boost cells connected to a common node of the boosted word line, and a timing control circuit. The stages of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node to provide an intermediate voltage to the boosted word line during the pre-boost timing, thereby anticipating a final boosted word line voltage provided during the boost timing. The voltage boost circuit is operable to receive the one or more output signals from the supply voltage detection circuit and alter a boost gain of the multi-stage voltage boost circuit based on the one or more output signals, thereby causing the boosted word line voltage to be substantially independent of the supply voltage value.
摘要翻译：公开了闪存阵列系统和方法，用于产生用于读取操作的稳压升压字线电压。该系统包括多级升压电路，其可操作以从电源电压检测电路接收电源电压和一个或多个输出信号，以产生具有大于电源电压的值的升压字线电压。升压电路包括预充电电路和连接到升压字线的公共节点的多个升压单元以及定时控制电路。多个升压单元的级级串联耦合，用于级之间的电荷共享，并且将预定数量的升压单元耦合到升压字线公共节点，以在预升压定时期间向升压的字线提供中间电压从而预期在升压定时期间提供的最后升高的字线电压。电压升压电路可操作以从电源电压检测电路接收一个或多个输出信号，并且基于一个或多个输出信号改变多级升压电路的升压增益，从而使升压的字线电压基本上不依赖于电源电压值。

2. 发明授权

US06781417B1 Buffer driver circuit for producing a fast, stable, and accurate reference voltage 有权
标题翻译：缓冲驱动电路，用于产生快速，稳定，准确的参考电压
公开(公告)号：US06781417B1
公开(公告)日：2004-08-24
申请号：US10282459
申请日：2002-10-29
申请人： Binh Quang Le , Lee Cleveland , Pau-Ling Chen
发明人： Binh Quang Le , Lee Cleveland , Pau-Ling Chen
IPC分类号： H03K19185
CPC分类号： G05F3/242 , H03K19/018507
摘要： According to one exemplary embodiment, a buffer circuit is configured to receive a supply voltage and an input reference voltage, the buffer circuit has a first FET operating in saturation region where the source of the first FET is coupled to the output reference voltage. The first FET can be configured, for example, as an open-loop voltage follower and, by way of example, a first resistor can be used to couple the source of the first FET to the output reference voltage. A tracking circuit is connected to the buffer circuit. The tracking circuit comprises a second FET also operating in saturation region where the drain of the second FET is coupled to the output reference voltage. Both the first and second FETs can be, for example, depletion mode transistors.
摘要翻译：根据一个示例性实施例，缓冲电路被配置为接收电源电压和输入参考电压，所述缓冲电路具有在饱和区域中工作的第一FET，其中第一FET的源极耦合到输出参考电压。第一FET可以被配置为例如开环电压跟随器，并且作为示例，可以使用第一电阻器将第一FET的源极耦合到输出参考电压。跟踪电路连接到缓冲电路。跟踪电路包括也在饱和区域工作的第二FET，其中第二FET的漏极耦合到输出参考电压。第一和第二FET都可以是例如耗尽型晶体管。

3. 发明授权

US06894473B1 Fast bandgap reference circuit for use in a low power supply A/D booster 有权
标题翻译：用于低电源A / D加速器的快速带隙基准电路
公开(公告)号：US06894473B1
公开(公告)日：2005-05-17
申请号：US10379744
申请日：2003-03-05
申请人： Binh Quang Le , Cathy Thuvan Ly , Lee Cleveland , Pau-Ling Chen
发明人： Binh Quang Le , Cathy Thuvan Ly , Lee Cleveland , Pau-Ling Chen
IPC分类号： G05F3/16 , G05F3/30
CPC分类号： G05F3/30
摘要： A bandgap reference circuit includes a current generation circuit connected to a voltage generation circuit connected to a smart clamping circuit, and a discharge circuit connected to the current generation circuit and the voltage generation circuit. The discharge circuit initially discharges a potential in the current and voltage generation circuits to improve repeatability. A start circuit within the current generation circuit then initializes the reference output at about the supply voltage to improve the speed and settling time of the output signal. The current generation circuit sources a current to the voltage generation circuit that translates the current having a positive function of temperature +TC into a reference voltage. The smart clamping circuit further generates a clamping voltage having a negative function of temperature −TC and a load resistance. The clamping voltage and the load resistance are applied across the reference voltage quickly reducing the reference voltage particularly at high temperatures and during start-up to a final level, thereby producing a fast and stable reference voltage.
摘要翻译：带隙基准电路包括与连接到智能钳位电路的电压产生电路连接的电流产生电路和连接到电流产生电路和电压产生电路的放电电路。放电电路最初在电流和电压产生电路中释放电位以改善重复性。然后，当前发电电路中的启动电路在大约电源电压下初始化参考输出，以提高输出信号的速度和稳定时间。电流产生电路将电流输出到电压产生电路，其将具有温度+ T C C的正函数的电流转换为参考电压。智能钳位电路进一步产生具有温度-T T C的负功能和负载电阻的钳位电压。钳位电压和负载电阻跨越参考电压施加，特别是在高温下和启动期间快速降低参考电压，从而产生快速稳定的参考电压。

4. 发明授权

US07076703B1 Method and system for defining a redundancy window around a particular column in a memory array 有权
标题翻译：用于在存储器阵列中的特定列周围定义冗余窗口的方法和系统
公开(公告)号：US07076703B1
公开(公告)日：2006-07-11
申请号：US10305700
申请日：2002-11-26
申请人： Binh Quang Le , Pau-Ling Chen
发明人： Binh Quang Le , Pau-Ling Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/804
摘要： A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.
摘要翻译：一种用于存储器冗余的方法，包括通常具有存储器单元的多个列（例如，位线）的存储器阵列，以及识别存储器阵列的特定（例如，有缺陷的）列，并进一步通过选择一个一组相邻列，包括有缺陷的列。所选列组中的列数可以等于耦合到存储器阵列的冗余阵列中的列数。冗余阵列用于存储否则将存储在冗余窗口中的存储器单元中的信息。所选择的组包括在缺陷列的一侧上的至少一个列和在缺陷列的另一侧上的另一个列。通常，有缺陷的列的每一侧将有多个列。

5. 发明授权

US06288951B1 Method and apparatus for continuously regulating a charge pump output voltage using a capacitor divider 有权
标题翻译：使用电容分压器连续调节电荷泵输出电压的方法和装置
公开(公告)号：US06288951B1
公开(公告)日：2001-09-11
申请号：US09675940
申请日：2000-09-29
申请人： Pau-Ling Chen , Binh Quang Le
发明人： Pau-Ling Chen , Binh Quang Le
IPC分类号： G11C700
CPC分类号： G11C5/145
摘要： A non-volatile memory and method for continuously regulating an output of a charge pump of the non-volatile memory for long periods of time at a target output voltage.
摘要翻译：一种非易失性存储器和方法，用于在目标输出电压下长时间持续地调节非易失性存储器的电荷泵的输出。

6. 发明授权

US06262469B1 Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor 失效
标题翻译：用于具有浮置晶体管作为相应电容器的电容分压器中的电容器
公开(公告)号：US06262469B1
公开(公告)日：2001-07-17
申请号：US09047237
申请日：1998-03-25
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer
IPC分类号： H01L2900
CPC分类号： H01L29/94 , H01L27/0811 , H01L29/66189
摘要： A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.
摘要翻译：电容器分压器包括两个电容器，它们串联在两个电压源之间。第一电容器是浮置栅极电容器，其中一个板是浮栅晶体管结构的控制栅极，另一个栅极是浮栅晶体管结构的源极，漏极和沟道区。电容分压器的优点是具有至少一个浮置栅极电容器，可以在电压调节器中实现，并且可以用于跨越电容器的各种电压。

7. 发明授权

US5999452A Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory 失效
标题翻译：双源多晶硅选择门结构和编程方法，利用单隧道氧化物进行NAND阵列闪存
公开(公告)号：US5999452A
公开(公告)日：1999-12-07
申请号：US63688
申请日：1998-04-21
申请人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译：串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。串联选择晶体管连接到NAND串中的最后一个晶体管。源选择晶体管连接到阵列Vss电源。为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

8. 发明授权

US5995417A Scheme for page erase and erase verify in a non-volatile memory array 有权
标题翻译：在非易失性存储器阵列中进行页擦除和擦除验证的方案
公开(公告)号：US5995417A
公开(公告)日：1999-11-30
申请号：US175646
申请日：1998-10-20
申请人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
发明人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
IPC分类号： G11C16/02 , G11C16/16 , G11C16/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.
摘要翻译：非易失性存储器件包括连接到各个字线16和18的多个MOS晶体管34和36，以允许存储在相应字线16和18上的存储器单元8a，10a和8b，10b中的存储器的各页被擦除和擦除验证。擦除一页存储单元的方法包括以下步骤：将擦除电压施加到MOS晶体管16和18中的一个以擦除沿着相应字线的存储单元的页面，并将初始擦除禁止浮动电压施加到其他连接到未选择用于页面擦除的字线的MOS晶体管。在擦除验证模式下，擦除验证电压被施加到在擦除模式下被选择用于页擦除的字线，并且擦除验证未选择电压被施加到未被选择用于页擦除的字线。

9. 发明授权

US5912489A Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory 失效
标题翻译：双源端多晶硅选择门结构利用单隧道氧化物用于NAND阵列闪存
公开(公告)号：US5912489A
公开(公告)日：1999-06-15
申请号：US940674
申请日：1997-09-30
申请人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译：串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。串联选择晶体管连接到NAND串中的最后一个晶体管。源选择晶体管连接到阵列Vss电源。为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

10. 发明授权

US06791880B1 Non-volatile memory read circuit with end of life simulation 有权
标题翻译：非易失性存储器读取电路，具有寿命终止模拟
公开(公告)号：US06791880B1
公开(公告)日：2004-09-14
申请号：US10431320
申请日：2003-05-06
申请人： Kazuhiro Kurihara , Binh Quang Le , Pau-Ling Chen , Darlene Hamilton , Edward Hsia
发明人： Kazuhiro Kurihara , Binh Quang Le , Pau-Ling Chen , Darlene Hamilton , Edward Hsia
IPC分类号： G11C1606
CPC分类号： G11C29/026 , G11C16/04 , G11C16/349 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C2029/5006
摘要： A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.
摘要翻译：具有可调节电流源以提供寿命终止模拟的非易失性存储器读取电路。包括用于提供用于与正在读取的存储器单元的电流进行比较的参考电流的参考电流源的闪速存储器件包括与被读取的存储器单元并联的可调电流源，以及与可读电流源并联的可调电流源参考电流源。来自存储单元，参考电流源及其并联可调电流源的电流被输入到共源共栅电路，用于转换成由读出放大器比较的电压。可以通过调节可调电流源来评估级联电路和读出放大器响应于存储器单元和参考电流源的变化的行为，使得在读出放大器的每个输入处的组合电流在老化之后模拟电路的电流或骑自行车。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式