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1. 发明授权

US08611379B2 Resonant clock amplifier with a digitally tunable delay 有权
标题翻译：具有数字可调延迟的谐振时钟放大器
公开(公告)号：US08611379B2
公开(公告)日：2013-12-17
申请号：US13094484
申请日：2011-04-26
申请人： Bharath Raghavan , Jun Cao , Afshin Momtaz
发明人： Bharath Raghavan , Jun Cao , Afshin Momtaz
IPC分类号： H04J3/04
CPC分类号： H03K5/07 , H03K2005/00071 , H03K2005/00208 , H03M9/00 , H04L7/0079 , H04L7/02 , H04L7/027 , H04L7/033
摘要： A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.
摘要翻译：可编程频率接收机包括用于以第一频率接收数据的分片器，用于以第二频率解复用数据的解复用器，用于产生第一频率的时钟的可编程时钟发生器，以及第一和第二谐振时钟放大器用于在第一和第二频率处放大时钟信号。谐振时钟放大器包括具有低Q值的电感器，允许它们在接收器的可编程频率范围上放大时钟信号。第二谐振时钟放大器包括数字可调谐延迟元件，以在限幅器和解复用器之间的接口处在数据窗口中延迟和居中放大的第二频率的时钟信号。延迟元件可以是电容器。校准电路调整主时钟发生器内的电容元件，以产生第一个频率的主时钟。

2. 发明申请

US20120027074A1 Summer Block For A Decision Feedback Equalizer 失效
标题翻译：决策反馈均衡器的夏季块
公开(公告)号：US20120027074A1
公开(公告)日：2012-02-02
申请号：US12878689
申请日：2010-09-09
申请人： Bharath RAGHAVAN , Afshin Momtaz , Jun Cao
发明人： Bharath RAGHAVAN , Afshin Momtaz , Jun Cao
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L25/03885 , H04L25/061 , H04L25/10 , H04L2025/03356 , H04L2025/03382 , H04L2025/03503
摘要： Embodiments of a summer block for a Decision Feedback Equalizer are provided herein. The summer block is configured to offset a combination of a Feed Forward Equalized (FFE) data signal and a Feedback Equalized (FBE) data signal by a dc amount. The dc amount is based on at least a weight of a tap previously implemented with an FBE of the DFE. The summer block can be further configured to offset the combination of the FFE data signal and the FBE data signal based on a dc offset value necessary to compensate for asymmetries in the data eye of data received by the FFE over a channel and a dc offset value necessary to compensate for mismatches present in the circuits of the DFE.
摘要翻译：本文提供了用于判决反馈均衡器的加法块的实施例。加法块被配置为通过直流量偏移前馈均衡（FFE）数据信号和反馈均衡（FBE）数据信号的组合。直流量基于以前用DFE的FBE实现的抽头的重量。加法块可以进一步配置为基于补偿由FFE在信道上接收的数据的数据眼中的不对称所必需的直流偏移值和直流偏移值来补偿FFE数据信号和FBE数据信号的组合必须补偿DFE电路中存在的不匹配。

3. 发明授权

US08457190B2 Summer block for a decision feedback equalizer 失效
标题翻译：夏季块决策反馈均衡器
公开(公告)号：US08457190B2
公开(公告)日：2013-06-04
申请号：US12878689
申请日：2010-09-09
申请人： Bharath Raghavan , Afshin Momtaz , Jun Cao
发明人： Bharath Raghavan , Afshin Momtaz , Jun Cao
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H04L25/03885 , H04L25/061 , H04L25/10 , H04L2025/03356 , H04L2025/03382 , H04L2025/03503
摘要： Embodiments of a summer block for a Decision Feedback Equalizer are provided herein. The summer block is configured to offset a combination of a Feed Forward Equalized (FFE) data signal and a Feedback Equalized (FBE) data signal by a dc amount: The dc amount is based on at least a weight of a tap previously implemented with an FBE of the DFE. The summer block can be further configured to offset the combination of the FFE data signal and the FBE data signal based on a dc offset value necessary to compensate for asymmetries in the data eye of data received by the FFE over a channel and a dc offset value necessary to compensate for mismatches present in the circuits of the DFE.
摘要翻译：本文提供了用于判决反馈均衡器的加法块的实施例。加法块被配置为通过直流量偏移前馈均衡（FFE）数据信号和反馈均衡（FBE）数据信号的组合。直流量基于以前用DFE的FBE实现的抽头的重量。加法块可以进一步配置为基于补偿由FFE在信道上接收的数据的数据眼中的不对称所必需的直流偏移值和直流偏移值来补偿FFE数据信号和FBE数据信号的组合必须补偿DFE电路中存在的不匹配。

4. 发明申请

US20120044958A1 RESONANT CLOCK AMPLIFIER WITH A DIGITALLY TUNABLE DELAY 有权
标题翻译：具有数字可调延时功能的谐振时钟放大器
公开(公告)号：US20120044958A1
公开(公告)日：2012-02-23
申请号：US13094484
申请日：2011-04-26
申请人： Bharath Raghavan , Jun Cao , Afshin Momtaz
发明人： Bharath Raghavan , Jun Cao , Afshin Momtaz
IPC分类号： H04B1/06 , H04B1/02
CPC分类号： H03K5/07 , H03K2005/00071 , H03K2005/00208 , H03M9/00 , H04L7/0079 , H04L7/02 , H04L7/027 , H04L7/033
摘要： A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.
摘要翻译：可编程频率接收机包括用于以第一频率接收数据的分片器，用于以第二频率解复用数据的解复用器，用于产生第一频率的时钟的可编程时钟发生器，以及第一和第二谐振时钟放大器用于在第一和第二频率处放大时钟信号。谐振时钟放大器包括具有低Q值的电感器，允许它们在接收器的可编程频率范围上放大时钟信号。第二谐振时钟放大器包括数字可调谐延迟元件，以在限幅器和解复用器之间的接口处在数据窗口中延迟和居中放大的第二频率的时钟信号。延迟元件可以是电容器。校准电路调整主时钟发生器内的电容元件，以产生第一个频率的主时钟。

5. 发明授权

US08077060B2 Distributed threshold adjustment for high speed receivers 有权
标题翻译：高速接收机的分布式阈值调整
公开(公告)号：US08077060B2
公开(公告)日：2011-12-13
申请号：US12582442
申请日：2009-10-20
申请人： Afshin Momtaz , Namik K. Kocaman , Bharath Raghavan
发明人： Afshin Momtaz , Namik K. Kocaman , Bharath Raghavan
IPC分类号： H03M7/00
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2203/45686
摘要： According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.
摘要翻译：根据一个一般方面，装置可以包括被配置为接收模拟输入信号的终端。在各种实施例中，该装置还可以包括多级放大器，其被配置为将模拟输入信号放大一定量的增益。在一些实施例中，该装置可以包括散布在多级放大器的级之间的分布式阈值调节器，其被配置为调整模拟输入信号的DC电压以便于模数转换器（ADC）的决定。在一个实施例中，该装置可以包括被配置为将放大的模拟输入信号转换成数字输出信号的ADC。

6. 发明申请

US20110291757A1 DISTRIBUTED THRESHOLD ADJUSTMENT FOR HIGH SPEED RECEIVERS 有权
标题翻译：高速接收机的分布式阈值调整
公开(公告)号：US20110291757A1
公开(公告)日：2011-12-01
申请号：US13207887
申请日：2011-08-11
申请人： Afshin Momtaz , Namik Kocaman , Bharath Raghavan
发明人： Afshin Momtaz , Namik Kocaman , Bharath Raghavan
IPC分类号： H03G3/20
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2203/45686
摘要： According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.
摘要翻译：根据一个一般方面，分布式阈值调节器（DTA）可以分散在多级放大器的级之间，以调节输入信号的直流电压。 DTA可以包括被配置为接收输入信号的输入信号端子。 DTA还可以包括多个电流源，其被配置为产生调节电流信号，其安培数被配置为通过固定步长增加或减小，以便调节输入信号的直流电压。 DTA可以包括控制单元，其被配置为选择性地打开或关闭多个电流源的各个电流源，以选择调节电流信号的电流强度。 DTA还可以包括输出端子，其被配置为产生包括输入信号和调整电流信号的组合的输出信号到多级放大器的级。

7. 发明申请

US20100271120A1 DISTRIBUTED THRESHOLD ADJUSTMENT FOR HIGH SPEED RECEIVERS 有权
标题翻译：高速接收机的分布式阈值调整
公开(公告)号：US20100271120A1
公开(公告)日：2010-10-28
申请号：US12582442
申请日：2009-10-20
申请人： Afshin Momtaz , Namik Kocaman , Bharath Raghavan
发明人： Afshin Momtaz , Namik Kocaman , Bharath Raghavan
IPC分类号： H03F1/00
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2203/45686
摘要： According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.
摘要翻译：根据一个一般方面，装置可以包括被配置为接收模拟输入信号的终端。在各种实施例中，该装置还可以包括多级放大器，其被配置为将模拟输入信号放大一定量的增益。在一些实施例中，该装置可以包括散布在多级放大器的级之间的分布式阈值调节器，其被配置为调整模拟输入信号的DC电压以便于模数转换器（ADC）的决定。在一个实施例中，该装置可以包括被配置为将放大的模拟输入信号转换成数字输出信号的ADC。

8. 发明授权

US08618964B2 Distributed threshold adjustment for high speed receivers 有权
标题翻译：高速接收机的分布式阈值调整
公开(公告)号：US08618964B2
公开(公告)日：2013-12-31
申请号：US13207887
申请日：2011-08-11
申请人： Afshin Momtaz , Namik Kocaman , Bharath Raghavan
发明人： Afshin Momtaz , Namik Kocaman , Bharath Raghavan
IPC分类号： H03M1/06
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2203/45686
摘要： According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.
摘要翻译：根据一个一般方面，分布式阈值调节器（DTA）可以分散在多级放大器的级之间，以调节输入信号的直流电压。 DTA可以包括被配置为接收输入信号的输入信号端子。 DTA还可以包括多个电流源，其被配置为产生调节电流信号，其安培数被配置为通过固定步长增加或减小，以便调节输入信号的直流电压。 DTA可以包括控制单元，其被配置为选择性地打开或关闭多个电流源的各个电流源，以选择调节电流信号的电流强度。 DTA还可以包括输出端子，其被配置为产生包括输入信号和调整电流信号的组合的输出信号到多级放大器的级。

9. 发明申请

US20120328063A1 Low Latency High Bandwidth CDR Architecture 有权
标题翻译：低延迟高带宽CDR体系结构
公开(公告)号：US20120328063A1
公开(公告)日：2012-12-27
申请号：US13168861
申请日：2011-06-24
申请人： Anand Jitendra Vasani , Jun Cao , Afshin Momtaz
发明人： Anand Jitendra Vasani , Jun Cao , Afshin Momtaz
IPC分类号： H04L7/02
CPC分类号： H04L7/0079 , H03L7/0812 , H04L7/033
摘要： Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.
摘要翻译：提供了低延迟高带宽时钟和数据恢复（CDR）系统。例如，存在低延迟高带宽CDR系统，其包括解复用器，其被配置为根据第一等待时间将高频输入数据流转换为低频输出数据流，并且相位误差处理器至少部分地被嵌入到解复用器中并且被配置为确定根据第二等待时间，高频输入数据流的数据流相位误差。嵌入式相位误差处理器允许由于解复用器和相位误差处理器而导致的CDR系统的总等待时间的一部分小于第一和第二延迟的和。

10. 发明申请

US20080150772A1 Apparatus and method for analog-to-digital converter calibration 有权
标题翻译：用于模数转换器校准的装置和方法
公开(公告)号：US20080150772A1
公开(公告)日：2008-06-26
申请号：US12000757
申请日：2007-12-17
申请人： Jun Cao , Afshin Momtaz
发明人： Jun Cao , Afshin Momtaz
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/362
摘要： Methods, systems, and apparatuses for calibration of analog to digital converters (ADC) are described herein. In an aspect, an ADC includes a plurality of slices. Each slice includes a digital to analog converter (DAC), a comparator, and a digital processing unit (DPU). The digital processing unit is electrically connected to the comparator and the DAC. In another aspect, an analog-to-digital converter includes an input module and an analog to digital converter core configured to receive an analog input from the input module and generate a digital output. The ADC is configured to adjust a precision of the analog to digital converter core based on a quality of the analog input signal.
摘要翻译：本文描述了用于模数转换器（ADC）的校准的方法，系统和装置。在一方面，ADC包括多个切片。每个片包括数模转换器（DAC），比较器和数字处理单元（DPU）。数字处理单元电连接到比较器和DAC。在另一方面，模数转换器包括被配置为从输入模块接收模拟输入并产生数字输出的输入模块和模数转换器内核。 ADC配置为基于模拟输入信号的质量来调整模数转换器内核的精度。

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