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1. 发明授权

US08611379B2 Resonant clock amplifier with a digitally tunable delay 有权
标题翻译：具有数字可调延迟的谐振时钟放大器
公开(公告)号：US08611379B2
公开(公告)日：2013-12-17
申请号：US13094484
申请日：2011-04-26
申请人： Bharath Raghavan , Jun Cao , Afshin Momtaz
发明人： Bharath Raghavan , Jun Cao , Afshin Momtaz
IPC分类号： H04J3/04
CPC分类号： H03K5/07 , H03K2005/00071 , H03K2005/00208 , H03M9/00 , H04L7/0079 , H04L7/02 , H04L7/027 , H04L7/033
摘要： A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.
摘要翻译：可编程频率接收机包括用于以第一频率接收数据的分片器，用于以第二频率解复用数据的解复用器，用于产生第一频率的时钟的可编程时钟发生器，以及第一和第二谐振时钟放大器用于在第一和第二频率处放大时钟信号。谐振时钟放大器包括具有低Q值的电感器，允许它们在接收器的可编程频率范围上放大时钟信号。第二谐振时钟放大器包括数字可调谐延迟元件，以在限幅器和解复用器之间的接口处在数据窗口中延迟和居中放大的第二频率的时钟信号。延迟元件可以是电容器。校准电路调整主时钟发生器内的电容元件，以产生第一个频率的主时钟。

2. 发明申请

US20100271120A1 DISTRIBUTED THRESHOLD ADJUSTMENT FOR HIGH SPEED RECEIVERS 有权
标题翻译：高速接收机的分布式阈值调整
公开(公告)号：US20100271120A1
公开(公告)日：2010-10-28
申请号：US12582442
申请日：2009-10-20
申请人： Afshin Momtaz , Namik Kocaman , Bharath Raghavan
发明人： Afshin Momtaz , Namik Kocaman , Bharath Raghavan
IPC分类号： H03F1/00
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2203/45686
摘要： According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.
摘要翻译：根据一个一般方面，装置可以包括被配置为接收模拟输入信号的终端。在各种实施例中，该装置还可以包括多级放大器，其被配置为将模拟输入信号放大一定量的增益。在一些实施例中，该装置可以包括散布在多级放大器的级之间的分布式阈值调节器，其被配置为调整模拟输入信号的DC电压以便于模数转换器（ADC）的决定。在一个实施例中，该装置可以包括被配置为将放大的模拟输入信号转换成数字输出信号的ADC。

3. 发明授权

US08457190B2 Summer block for a decision feedback equalizer 失效
标题翻译：夏季块决策反馈均衡器
公开(公告)号：US08457190B2
公开(公告)日：2013-06-04
申请号：US12878689
申请日：2010-09-09
申请人： Bharath Raghavan , Afshin Momtaz , Jun Cao
发明人： Bharath Raghavan , Afshin Momtaz , Jun Cao
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H04L25/03885 , H04L25/061 , H04L25/10 , H04L2025/03356 , H04L2025/03382 , H04L2025/03503
摘要： Embodiments of a summer block for a Decision Feedback Equalizer are provided herein. The summer block is configured to offset a combination of a Feed Forward Equalized (FFE) data signal and a Feedback Equalized (FBE) data signal by a dc amount: The dc amount is based on at least a weight of a tap previously implemented with an FBE of the DFE. The summer block can be further configured to offset the combination of the FFE data signal and the FBE data signal based on a dc offset value necessary to compensate for asymmetries in the data eye of data received by the FFE over a channel and a dc offset value necessary to compensate for mismatches present in the circuits of the DFE.
摘要翻译：本文提供了用于判决反馈均衡器的加法块的实施例。加法块被配置为通过直流量偏移前馈均衡（FFE）数据信号和反馈均衡（FBE）数据信号的组合。直流量基于以前用DFE的FBE实现的抽头的重量。加法块可以进一步配置为基于补偿由FFE在信道上接收的数据的数据眼中的不对称所必需的直流偏移值和直流偏移值来补偿FFE数据信号和FBE数据信号的组合必须补偿DFE电路中存在的不匹配。

4. 发明申请

US20120044958A1 RESONANT CLOCK AMPLIFIER WITH A DIGITALLY TUNABLE DELAY 有权
标题翻译：具有数字可调延时功能的谐振时钟放大器
公开(公告)号：US20120044958A1
公开(公告)日：2012-02-23
申请号：US13094484
申请日：2011-04-26
申请人： Bharath Raghavan , Jun Cao , Afshin Momtaz
发明人： Bharath Raghavan , Jun Cao , Afshin Momtaz
IPC分类号： H04B1/06 , H04B1/02
CPC分类号： H03K5/07 , H03K2005/00071 , H03K2005/00208 , H03M9/00 , H04L7/0079 , H04L7/02 , H04L7/027 , H04L7/033
摘要： A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.
摘要翻译：可编程频率接收机包括用于以第一频率接收数据的分片器，用于以第二频率解复用数据的解复用器，用于产生第一频率的时钟的可编程时钟发生器，以及第一和第二谐振时钟放大器用于在第一和第二频率处放大时钟信号。谐振时钟放大器包括具有低Q值的电感器，允许它们在接收器的可编程频率范围上放大时钟信号。第二谐振时钟放大器包括数字可调谐延迟元件，以在限幅器和解复用器之间的接口处在数据窗口中延迟和居中放大的第二频率的时钟信号。延迟元件可以是电容器。校准电路调整主时钟发生器内的电容元件，以产生第一个频率的主时钟。

5. 发明申请

US20120038390A1 GIGABIT-SPEED SLICER LATCH WITH HYSTERESIS OPTIMIZATION 失效
标题翻译：具有迟滞优化的GIGABIT-SPEED SLICER LATCH
公开(公告)号：US20120038390A1
公开(公告)日：2012-02-16
申请号：US12900986
申请日：2010-10-08
申请人： Bharath Raghavan
发明人： Bharath Raghavan
IPC分类号： H03K17/00 , H03K3/00
CPC分类号： H03K3/356043 , H03K3/012
摘要： Improved master latch for high-speed slicer providing enhanced input signal sensitivity. A pre-charging circuit injects charge into the sources of the differential pair of a latch that samples the input signal during odd clock cycles. This reduces the gate-to-source voltage of the sampling pair, making them less sensitive to data bits latched by a second parallel master latch in odd clock cycles. The injected charge dissipates before the sampling pair is needed to fully sample the input signal in even clock cycles. The pre-charging circuit includes a current mirror, a current source and a transistor that couples the current source to the current mirror during odd clock cycles. A shunt peaked amplifier with excess peaking boosts the high-frequency content of a differential input signal relative to its low-frequency content. Capacitors cross-couple the gates and drains of the differential sampling pair. These supply an equal but opposite gate current than supplied by the intrinsic gate-to-drain capacitance, thereby reducing net current to the gate, and jitter on the input signal.
摘要翻译：改进了高速切片器的主锁存器，提供增强的输入信号灵敏度。预充电电路将电荷注入到在奇数时钟周期期间对输入信号进行采样的锁存器的差分对的源极。这降低了采样对的栅极到源极电压，使得它们在奇数时钟周期内对由第二并行主锁存器锁存的数据位不敏感。在需要采样对之前，注入的电荷消耗在甚至时钟周期内完全采样输入信号。预充电电路包括电流镜，电流源和在奇数时钟周期期间将电流源耦合到电流镜的晶体管。具有过高峰值的并联峰值放大器相对于其低频内容提高了差分输入信号的高频内容。电容器交叉耦合差分采样对的栅极和漏极。它们提供与由本征栅极 - 漏极电容提供的栅极电流相等但相反的栅极电流，从而减小到栅极的净电流和输入信号的抖动。

6. 发明申请

US20100201340A1 LOW-SWING DIFFERENTIAL SIGNAL OUTPUT DRIVER WITH WIDE-RANGE SUPPLY VOLTAGE OPERABILITY 有权
标题翻译：具有宽范围供电电压运行的低电压差分信号输出驱动器
公开(公告)号：US20100201340A1
公开(公告)日：2010-08-12
申请号：US12369152
申请日：2009-02-11
申请人： Bharath Raghavan
发明人： Bharath Raghavan
IPC分类号： G05F3/00
CPC分类号： H03K19/018521
摘要： According to one general aspect, an output driver configured to drive output signals from a core device may include a voltage convertor, an output stage, and a biasing unit. In various embodiments, the output driver is configured to operate in either a core device voltage mode or a high voltage mode. In some embodiments, the voltage convertor may be configured to receive a pair of differential input signals from a core device, wherein a maximum voltage of the input signals is equivalent to a core device voltage, and convert the input signals to a pair of intermediate input signals. In one embodiment, when in high voltage mode, the maximum voltage of the intermediate input signals may be equivalent to a high voltage that is higher than the core device voltage. In some embodiments, the output stage configured to receive the intermediate input signals, and produce a pair of differential output signals having a maximum voltage of, based upon the operating mode of the output driver, either the core device voltage or the high voltage. In various embodiments, the biasing unit configured to provide a biasing current to the output stage, wherein the biasing current is configured to produce a desired common mode voltage within the output stage.
摘要翻译：根据一个一般方面，被配置为驱动来自核心设备的输出信号的输出驱动器可以包括电压转换器，输出级和偏置单元。在各种实施例中，输出驱动器被配置为以核心器件电压模式或高电压模式工作。在一些实施例中，电压转换器可以被配置为从核心器件接收一对差分输入信号，其中输入信号的最大电压等于核心器件电压，并将输入信号转换成一对中间输入信号。在一个实施例中，当处于高电压模式时，中间输入信号的最大电压可以等于高于核心器件电压的高电压。在一些实施例中，输出级被配置为接收中间输入信号，并且基于输出驱动器的操作模式产生具有最大电压的一对差分输出信号，即核心器件电压或高电压。在各种实施例中，偏置单元被配置为向输出级提供偏置电流，其中偏置电流被配置为在输出级内产生期望的共模电压。

7. 发明授权

US08698532B2 Gigabit-speed slicer latch with hysteresis optimization 失效
标题翻译：具有迟滞优化的千兆速度切片器锁存器
公开(公告)号：US08698532B2
公开(公告)日：2014-04-15
申请号：US12900986
申请日：2010-10-08
申请人： Bharath Raghavan
发明人： Bharath Raghavan
IPC分类号： H03K3/356
CPC分类号： H03K3/356043 , H03K3/012
摘要： Improved master latch for high-speed slicer providing enhanced input signal sensitivity. A pre-charging circuit injects charge into the sources of the differential pair of a latch that samples the input signal during odd clock cycles. This reduces the gate-to-source voltage of the sampling pair, making them less sensitive to data bits latched by a second parallel master latch in odd clock cycles. The injected charge dissipates before the sampling pair is needed to fully sample the input signal in even clock cycles. The pre-charging circuit includes a current mirror, a current source and a transistor that couples the current source to the current mirror during odd clock cycles. A shunt peaked amplifier with excess peaking boosts the high-frequency content of a differential input signal relative to its low-frequency content. Capacitors cross-couple the gates and drains of the differential sampling pair. These supply an equal but opposite gate current than supplied by the intrinsic gate-to-drain capacitance, thereby reducing net current to the gate, and jitter on the input signal.
摘要翻译：改进了高速切片器的主锁存器，提供增强的输入信号灵敏度。预充电电路将电荷注入到在奇数时钟周期期间对输入信号进行采样的锁存器的差分对的源极。这降低了采样对的栅极到源极电压，使得它们在奇数时钟周期内对由第二并行主锁存器锁存的数据位不敏感。在需要采样对之前，注入的电荷消耗在甚至时钟周期内完全采样输入信号。预充电电路包括电流镜，电流源和在奇数时钟周期期间将电流源耦合到电流镜的晶体管。具有过高峰值的并联峰值放大器相对于其低频内容提高了差分输入信号的高频内容。电容器交叉耦合差分采样对的栅极和漏极。它们提供与由本征栅极 - 漏极电容提供的栅极电流相等但相反的栅极电流，从而减小到栅极的净电流和输入信号的抖动。

8. 发明授权

US08077060B2 Distributed threshold adjustment for high speed receivers 有权
标题翻译：高速接收机的分布式阈值调整
公开(公告)号：US08077060B2
公开(公告)日：2011-12-13
申请号：US12582442
申请日：2009-10-20
申请人： Afshin Momtaz , Namik K. Kocaman , Bharath Raghavan
发明人： Afshin Momtaz , Namik K. Kocaman , Bharath Raghavan
IPC分类号： H03M7/00
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2203/45686
摘要： According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.
摘要翻译：根据一个一般方面，装置可以包括被配置为接收模拟输入信号的终端。在各种实施例中，该装置还可以包括多级放大器，其被配置为将模拟输入信号放大一定量的增益。在一些实施例中，该装置可以包括散布在多级放大器的级之间的分布式阈值调节器，其被配置为调整模拟输入信号的DC电压以便于模数转换器（ADC）的决定。在一个实施例中，该装置可以包括被配置为将放大的模拟输入信号转换成数字输出信号的ADC。

9. 发明申请

US20110291757A1 DISTRIBUTED THRESHOLD ADJUSTMENT FOR HIGH SPEED RECEIVERS 有权
标题翻译：高速接收机的分布式阈值调整
公开(公告)号：US20110291757A1
公开(公告)日：2011-12-01
申请号：US13207887
申请日：2011-08-11
申请人： Afshin Momtaz , Namik Kocaman , Bharath Raghavan
发明人： Afshin Momtaz , Namik Kocaman , Bharath Raghavan
IPC分类号： H03G3/20
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2203/45686
摘要： According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.
摘要翻译：根据一个一般方面，分布式阈值调节器（DTA）可以分散在多级放大器的级之间，以调节输入信号的直流电压。 DTA可以包括被配置为接收输入信号的输入信号端子。 DTA还可以包括多个电流源，其被配置为产生调节电流信号，其安培数被配置为通过固定步长增加或减小，以便调节输入信号的直流电压。 DTA可以包括控制单元，其被配置为选择性地打开或关闭多个电流源的各个电流源，以选择调节电流信号的电流强度。 DTA还可以包括输出端子，其被配置为产生包括输入信号和调整电流信号的组合的输出信号到多级放大器的级。

10. 发明授权

US07952397B2 Low-swing differential signal output driver with wide-range supply voltage operability 有权
标题翻译：低摆幅差分信号输出驱动器具有广泛的电源电压可操作性
公开(公告)号：US07952397B2
公开(公告)日：2011-05-31
申请号：US12369152
申请日：2009-02-11
申请人： Bharath Raghavan
发明人： Bharath Raghavan
IPC分类号： H03B1/00
CPC分类号： H03K19/018521
摘要： According to one general aspect, an output driver configured to drive output signals from a core device may include a voltage convertor, an output stage, and a biasing unit. In various embodiments, the output driver is configured to operate in either a core device voltage mode or a high voltage mode. In some embodiments, the voltage convertor may be configured to receive a pair of differential input signals from a core device, wherein a maximum voltage of the input signals is equivalent to a core device voltage, and convert the input signals to a pair of intermediate input signals. In one embodiment, when in high voltage mode, the maximum voltage of the intermediate input signals may be equivalent to a high voltage that is higher than the core device voltage. In some embodiments, the output stage configured to receive the intermediate input signals, and produce a pair of differential output signals having a maximum voltage of, based upon the operating mode of the output driver, either the core device voltage or the high voltage. In various embodiments, the biasing unit configured to provide a biasing current to the output stage, wherein the biasing current is configured to produce a desired common mode voltage within the output stage.
摘要翻译：根据一个一般方面，被配置为驱动来自核心设备的输出信号的输出驱动器可以包括电压转换器，输出级和偏置单元。在各种实施例中，输出驱动器被配置为以核心器件电压模式或高电压模式工作。在一些实施例中，电压转换器可以被配置为从核心器件接收一对差分输入信号，其中输入信号的最大电压等于核心器件电压，并将输入信号转换成一对中间输入信号。在一个实施例中，当处于高电压模式时，中间输入信号的最大电压可以等于高于核心器件电压的高电压。在一些实施例中，输出级被配置为接收中间输入信号，并且基于输出驱动器的操作模式产生具有最大电压的一对差分输出信号，即核心器件电压或高电压。在各种实施例中，偏置单元被配置为向输出级提供偏置电流，其中偏置电流被配置为在输出级内产生期望的共模电压。

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