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1. 发明授权

US07078348B1 Dual layer patterning scheme to make dual damascene 失效
标题翻译：双层图案方案制作双镶嵌
公开(公告)号：US07078348B1
公开(公告)日：2006-07-18
申请号：US09893188
申请日：2001-06-27
申请人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton
发明人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton
IPC分类号： H01L21/302 , H01L21/3065
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76811 , H01L21/76813
摘要： One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.
摘要翻译：本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法，该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。

2. 发明授权

US06629786B1 Active control of developer time and temperature 失效
标题翻译：主动控制显影时间和温度
公开(公告)号：US06629786B1
公开(公告)日：2003-10-07
申请号：US09845232
申请日：2001-04-30
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G03D500
CPC分类号： G03D5/00
摘要： A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译：提供了一种用于调节开发过程的时间和温度的系统。该系统包括一个或多个光源，每个光源将光引导到在晶片上显影的一个或多个光栅。从光栅反射的光被测量系统收集，该系统处理收集的光。通过光栅的光可以类似地由处理所收集的光的测量系统收集。所收集的光表示晶片的各个部分的显影进展。该测量系统提供开发相关数据的进展到处理器，该处理器确定晶片的相应部分的开发进度。该系统还包括多个加热装置，每个加热装置对应于显影剂的相应部分并提供其加热。处理器选择性地控制加热装置，以调节晶片各部分的温度。

3. 发明授权

US06613500B1 Reducing resist residue defects in open area on patterned wafer using trim mask 有权
标题翻译：使用修剪掩模减少图案化晶片上的开放区域中的抗蚀剂残留缺陷
公开(公告)号：US06613500B1
公开(公告)日：2003-09-02
申请号：US09824079
申请日：2001-04-02
申请人： Khoi A. Phan , Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton , Jeff Erhardt
发明人： Khoi A. Phan , Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton , Jeff Erhardt
IPC分类号： G03F700
CPC分类号： G03F7/70425 , G03F7/2022 , G03F7/203 , G03F7/70466
摘要： One aspect of the present invention relates to a method for reducing resist residue defects on a wafer structure. The method involves providing a semiconductor structure having a photoresist, the photoresist comprising open areas and circuit areas thereon; irradiating the open areas and circuit areas through a first photomask with a first energy dose to effect an image-wise pattern in the photoresist; irradiating the open areas of the photoresist through a second photomask with a second energy dose; and developing the photoresist.
摘要翻译：本发明的一个方面涉及减少晶片结构上的抗蚀剂残留缺陷的方法。该方法包括提供具有光致抗蚀剂的半导体结构，光致抗蚀剂包括开放区域和其上的电路区域; 通过具有第一能量剂量的第一光掩模照射开放区域和电路区域以在光致抗蚀剂中实现成像图案; 通过具有第二能量剂量的第二光掩模照射光致抗蚀剂的开放区域; 并显影光致抗蚀剂。

4. 发明授权

US06444381B1 Electron beam flood exposure technique to reduce the carbon contamination 有权
标题翻译：电子束泛滥技术减少碳污染
公开(公告)号：US06444381B1
公开(公告)日：2002-09-03
申请号：US09729295
申请日：2000-12-04
申请人： Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton , Bharath Rangarajan , Khoi A. Phan , Bryan K. Choo , Sanjay K. Yedur
发明人： Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton , Bharath Rangarajan , Khoi A. Phan , Bryan K. Choo , Sanjay K. Yedur
IPC分类号： G03F900
CPC分类号： G03F1/74 , Y10S430/143
摘要： One aspect of the present invention relates to a method for reducing carbon contamination on a mask involving placing a mask plate having carbon-containing contaminants thereon in a processing chamber; simultaneously contacting the mask plate with oxygen and exposing the mask plate with a flood exposure of electron beams wherein the carbon-containing contaminants are converted to a by-product; and removing the by-product from the processing chamber.
摘要翻译：本发明的一个方面涉及一种用于减少掩模上的碳污染的方法，其涉及将具有含碳污染物的掩模板放置在处理室中; 同时使掩模板与氧气接触，并将电子束的暴露暴露于掩模板，其中含碳污染物转化为副产物; 并从处理室中除去副产物。

5. 发明授权

US06335152B1 Use of RTA furnace for photoresist baking 有权
标题翻译：使用RTA炉进行光刻胶烘烤
公开(公告)号：US06335152B1
公开(公告)日：2002-01-01
申请号：US09564408
申请日：2000-05-01
申请人： Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh
发明人： Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh
IPC分类号： G03F738
CPC分类号： G03F7/38
摘要： In one embodiment, the present invention relates to a method of processing an irradiated photoresist involving the steps of placing a substrate having the irradiated photoresist thereon at a first temperature in a rapid thermal anneal furnace; heating the substrate having the irradiated photoresist thereon to a second temperature within about 0.1 seconds to about 10 seconds; cooling the substrate having the irradiated photoresist thereon to a third temperature in a rapid thermal annealing furnace within about 0.1 seconds to about 10 seconds; and developing the irradiated photoresist, wherein the second temperature is higher than the first temperature and the third temperature. In another embodiment, the present invention relates to a system of processing a photoresist, containing a source of actinic radiation and a mask for selectively irradiating a photoresist; a rapid thermal annealing furnace for rapidly heating and rapidly cooling a selectively irradiated photoresist, wherein the rapid heating and rapid cooling are independently conducted within about 0.1 seconds to about 10 seconds; and a developer for developing a rapid thermal annealing furnace heated and selectively irradiated photoresist into a patterned photoresist.
摘要翻译：在一个实施方案中，本发明涉及一种处理被照射的光致抗蚀剂的方法，包括以下步骤：在快速热退火炉中将具有照射光致抗蚀剂的基底在第一温度下放置; 将其上具有照射的光致抗蚀剂的基板加热至约0.1秒至约10秒的第二温度; 将快速热退火炉中具有照射光致抗蚀剂的基板冷却至约0.1秒至约10秒的第三温度; 并且显影所述被照射的光致抗蚀剂，其中所述第二温度高于所述第一温度和所述第三温度。在另一个实施方案中，本发明涉及一种处理含有光化辐射源的光致抗蚀剂的系统和用于选择性地照射光致抗蚀剂的掩模; 快速热退火炉，用于快速加热和快速冷却选择性照射的光致抗蚀剂，其中快速加热和快速冷却在约0.1秒至约10秒内独立进行; 以及用于将快速热退火炉加热并选择性地照射光致抗蚀剂的显影剂加工成图案化的光致抗蚀剂。

6. 发明授权

US06845345B1 System for monitoring and analyzing diagnostic data of spin tracks 失效
标题翻译：维护调度采用远程分析诊断数据
公开(公告)号：US06845345B1
公开(公告)日：2005-01-18
申请号：US09777435
申请日：2001-02-06
申请人： Bhanwar Singh , Michael K. Templeton , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Ramkumar Subramanian
IPC分类号： G06F11/00
CPC分类号： G05B23/0283
摘要： A system for analyzing diagnostic information associated with a spin track is provided. The system includes one or more analysis systems that collect diagnostic information from one or more spin tracks. The system further includes one or more maintenance systems that schedule routine and/or special maintenance based on analysis of the diagnostic information. An alternative aspect of the system further includes one or more control information systems that generate of feedback control information employed in adapting the processes performed by the spin track.
摘要翻译：提供了一种用于分析与自旋轨迹相关联的诊断信息的系统。该系统包括从一个或多个自旋轨道收集诊断信息的一个或多个分析系统。该系统还包括一个或多个维护系统，其基于对诊断信息的分析来调度例行和/或特殊维护。该系统的另一方面还包括一个或多个控制信息系统，其产生用于适应由旋转轨迹执行的处理的反馈控制信息。

7. 发明授权

US06641963B1 System and method for in situ control of post exposure bake time and temperature 失效
标题翻译：曝晒后烘烤时间和温度的现场控制系统和方法
公开(公告)号：US06641963B1
公开(公告)日：2003-11-04
申请号：US09845239
申请日：2001-04-30
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G03F900
CPC分类号： G03F7/38 , G03B27/52
摘要： A system for regulating temperature of a post exposure baking process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being baked and hardened on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the baking and hardening of the respective portions of the wafer. The measuring system provides baking and hardening related data to a processor that determines the baking and hardening of the respective portions of the wafer. The system also includes a plurality of temperature controlling devices, each such device corresponds to a respective portion of the wafer and provides for the heating and/or cooling thereof. The processor selectively controls the temperature controlling devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译：提供了一种用于调节后曝光烘烤处理温度的系统。该系统包括一个或多个光源，每个光源将光引导到在晶片上被烘烤和硬化的一个或多个光栅。从光栅反射的光被测量系统收集，该系统处理收集的光。通过光栅的光可以类似地由处理所收集的光的测量系统收集。所收集的光表示晶片的各个部分的烘烤和硬化。测量系统向处理器提供烘烤和硬化相关数据，该处理器确定晶片的相应部分的烘烤和硬化。该系统还包括多个温度控制装置，每个这样的装置对应于晶片的相应部分并提供其加热和/或冷却。处理器选择性地控制温度控制装置，以调节晶片各部分的温度。

8. 发明授权

US06630361B1 Use of scatterometry for in-situ control of gaseous phase chemical trim process 有权
标题翻译：使用散射法进行气相化学修饰过程的原位控制
公开(公告)号：US06630361B1
公开(公告)日：2003-10-07
申请号：US09894701
申请日：2001-06-28
申请人： Bhanwar Singh , Bharath Rangarajan , Michael K. Templeton , Ramkumar Subramanian , Cristina Cheung
发明人： Bhanwar Singh , Bharath Rangarajan , Michael K. Templeton , Ramkumar Subramanian , Cristina Cheung
IPC分类号： H01L2100
CPC分类号： H01L22/20 , G01N21/47 , G01N21/9501 , G01N21/956 , H01L21/67253
摘要： A system for regulating a gaseous phase chemical trim process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides trimming related data to a processor that determines the acceptability of the trimming of the respective portions of the wafer. The system also includes one or more trimming devices, each such device corresponding to a portion of the wafer and providing for the trimming thereof. The processor selectively controls the trimming devices to regulate trimming of the portions of the wafer.
摘要翻译：提供了一种用于调节气相化学修饰过程的系统。该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。所收集的光指示在晶片的相应部分处获得的尺寸。测量系统向处理器提供修剪相关数据，该处理器确定了晶片各部分的修整的可接受性。该系统还包括一个或多个修整装置，每个这样的装置对应于晶片的一部分并提供其修剪。处理器选择性地控制修整装置来调节对晶片的部分的修整。

9. 发明授权

US06605855B1 CVD plasma process to fill contact hole in damascene process 有权
标题翻译： CVD等离子体工艺在镶嵌工艺中填充接触孔
公开(公告)号：US06605855B1
公开(公告)日：2003-08-12
申请号：US09650538
申请日：2000-08-30
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
IPC分类号： H01L2900
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/312 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
摘要翻译：本发明涉及在绝缘材料层中制造互连线和通孔的方法。在绝缘材料层中形成通孔。形成保护材料以至少与通孔的边缘和侧壁共形，所述保护材料有助于屏蔽通孔的至少边缘和侧壁至沟槽蚀刻步骤。执行沟槽蚀刻步骤以在绝缘材料中形成沟槽开口。通孔和沟槽填充有导电金属。

10. 发明授权

US06545753B2 Using scatterometry for etch end points for dual damascene process 失效
标题翻译：使用散射法进行双镶嵌工艺的蚀刻终点
公开(公告)号：US06545753B2
公开(公告)日：2003-04-08
申请号：US09893186
申请日：2001-06-27
申请人： Ramkumar Subramanian , Bhanwar Singh , Michael K. Templeton
发明人： Ramkumar Subramanian , Bhanwar Singh , Michael K. Templeton
IPC分类号： G01N2100
CPC分类号： H01L21/7681 , G01N21/4738 , H01J37/32935
摘要： A system for monitoring and/or controlling an etch process associated with a dual damascene process via scatterometry based processing is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the desirability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor produces a real time feed forward information to control the etch process, in particular, terminating the etch process when desired end points have been encountered.
摘要翻译：提供了一种用于通过基于散射测量的处理来监测和/或控制与双镶嵌工艺相关联的蚀刻工艺的系统。该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。所收集的光指示在晶片的各个部分实现的蚀刻结果。测量系统向处理器提供蚀刻相关数据，该处理器确定晶片的相应部分的蚀刻的可取性。该系统还包括一个或多个蚀刻装置，每个这样的装置对应于晶片的一部分并提供其蚀刻。处理器产生实时前馈信息以控制蚀刻工艺，特别是在遇到所需端点时终止蚀刻工艺。

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